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FPGA & Verilog Design

Nandland / Digi-Key series · Hardware · Spring 2027 · Planned

Lectures

  1. Part 1: What is an FPGA? (15:20)
  2. Part 2: Getting Started with Yosys, IceStorm, and Apio (18:50)
  3. Part 3: Getting Started with Verilog (20:43)
  4. Part 4: Clocks and Procedural Assignments (18:09)
  5. Part 5: Finite State Machines (24:24)
  6. Part 6: Verilog Modules and Parameters (16:34)
  7. Part 7: Verilog Testbenches and Simulation (27:03)
  8. Part 8: Memory and Block RAM (27:32)
  9. Part 9: Phase-Locked Loop (PLL) and Glitches (23:28)
  10. Part 10: Metastability and Clock Domain Crossing (13:26)
  11. Part 11: RISC-V Softcore Processor (23:06)
  12. Part 12: RISC-V Custom Peripheral (23:46)

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