Part 10: Metastability and Clock Domain Crossing

What this lecture covers

This lecture addresses what can go wrong when a signal isn't safely aligned to the clock sampling it - a concern for asynchronous inputs and for any design using more than one clock. It explains setup and hold time, what metastability is, and why crossing between clock domains without care is risky.

By the end you can describe why a D flip-flop needs its input held steady around a clock edge, build a synchronizer from chained flip-flops, recognize why the series' earlier clock dividers were technically bad practice, build a better divider using a single "tick" pulse, and explain at a conceptual level how an asynchronous FIFO lets data cross clock domains safely. It closes the introductory portion of the series and previews building a RISC-V soft core processor next.

Key ideas

• Setup and hold time: a flip-flop's input must remain stable for a defined window before (setup) and after (hold) the clock edge; a change during that window is a timing violation.
• Metastability: a timing violation can leave a flip-flop's output in an unknown, unstable state for an indeterminate time before it settles - a probabilistic failure, not a deterministic one.
• Synchronizer: chaining two (or more) flip-flops in series on an asynchronous or cross-domain signal greatly reduces the chance that metastability propagates to the rest of the design, at the cost of one extra clock cycle of latency per stage.
• Clock domain: all logic clocked from one signal (or a divided version of it); crossing between domains without a synchronizer risks metastability.
• Bad clock divider practice: dividing a clock by feeding one flip-flop's output into another's clock input effectively creates a new, uncontrolled clock domain.
• Tick-based clock divider: instead of generating a divided clock signal, a counter produces a single-cycle "tick" pulse that the main clocked logic checks conditionally, keeping the whole design in one clock domain.
• Asynchronous FIFO: a dual-clocked block RAM-based queue (write clock and read clock) that lets data move safely between clock domains, using internal synchronizers on the read/write address pointers.

Walkthrough

Setup, hold time, and metastability (0:00)

The lecture defines the setup and hold windows around a flip-flop's clock edge, explains that a violation can cause metastability - an unpredictable, temporarily unstable output - and notes that this is probabilistic and generally too fast to observe directly on an oscilloscope, referencing an external experiment that demonstrates it by deliberately shifting clock phase.

Building a synchronizer (4:08)

The fix for sampling an asynchronous or cross-domain signal is a chain of flip-flops (a synchronizer): each additional stage reduces the chance that metastability reaches the final output, at the cost of extra clock-cycle latency.

Clock domains and why crossing them is risky (6:11)

The lecture defines a clock domain and explains clock domain crossing - sampling a signal generated by one clock (say, an external 5 MHz SPI signal) with logic clocked by another (the 12 MHz system clock) - as a common source of hard-to-debug, intermittent failures, recommending a synchronizer at the receiving domain and, where possible, avoiding domain crossings altogether.

A better clock divider design (7:14)

The lecture revisits the series' earlier clock dividers, noting that generating a divided clock signal from flip-flop outputs effectively creates an unmanaged second clock domain. The improved design instead counts up to a parameterized maximum and asserts a one-cycle "tick" output, which downstream logic checks with a simple conditional inside its existing clocked always block - keeping the whole design in a single, well-behaved clock domain.

Introducing FIFOs for clock domain crossing (9:20)

A FIFO (first-in, first-out queue) is introduced as a memory-based way to pass data between a sender and receiver safely: elements are read in the order written, and code must track full/empty conditions to avoid reading from an empty FIFO or writing to a full one.

Asynchronous FIFOs and the challenge (11:24)

Using the iCE40's dual-clock block RAM (separate read and write clocks) and Clifford Cummings' well-known FIFO design as a reference, the lecture explains how synchronizer circuits on the internal read/write address pointers make the FIFO safe to use across two independent clock domains. The challenge is to implement this FIFO in Verilog and write a test bench proving it correctly handles full and empty conditions.

Before you watch

• Complete Part 9 ("Phase-Locked Loop (PLL) and Glitches"); this lecture assumes familiarity with propagation delay and builds on that intuition for timing violations.
• Recall the clock dividers built in Parts 4 and 6, since this lecture explains why that earlier approach should be improved.

Check your understanding

1. What is the difference between a setup time violation and a hold time violation?
2. Why does adding a second flip-flop to a synchronizer reduce the risk of metastability reaching the rest of the design?
3. Why does the lecture consider the series' earlier clock-divider designs bad practice, and how does the tick-based divider avoid that problem?
4. What conditions must a FIFO implementation guard against to avoid corrupting its data?
5. Why does an asynchronous FIFO need synchronizers on its internal read and write address pointers?