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FPGA & Verilog Design · Lecture 10 of 12 · 13:26

Part 10: Metastability and Clock Domain Crossing

Study guide

What this lecture covers

This lecture addresses what can go wrong when a signal isn't safely aligned to the clock sampling it - a concern for asynchronous inputs and for any design using more than one clock. It explains setup and hold time, what metastability is, and why crossing between clock domains without care is risky.

By the end you can describe why a D flip-flop needs its input held steady around a clock edge, build a synchronizer from chained flip-flops, recognize why the series' earlier clock dividers were technically bad practice, build a better divider using a single "tick" pulse, and explain at a conceptual level how an asynchronous FIFO lets data cross clock domains safely. It closes the introductory portion of the series and previews building a RISC-V soft core processor next.

Key ideas

Setup and hold time: a flip-flop's input must remain stable for a defined window before (setup) and after (hold) the clock edge; a change during that window is a timing violation.
Metastability: a timing violation can leave a flip-flop's output in an unknown, unstable state for an indeterminate time before it settles - a probabilistic failure, not a deterministic one.
Synchronizer: chaining two (or more) flip-flops in series on an asynchronous or cross-domain signal greatly reduces the chance that metastability propagates to the rest of the design, at the cost of one extra clock cycle of latency per stage.
Clock domain: all logic clocked from one signal (or a divided version of it); crossing between domains without a synchronizer risks metastability.
Bad clock divider practice: dividing a clock by feeding one flip-flop's output into another's clock input effectively creates a new, uncontrolled clock domain.
Tick-based clock divider: instead of generating a divided clock signal, a counter produces a single-cycle "tick" pulse that the main clocked logic checks conditionally, keeping the whole design in one clock domain.
Asynchronous FIFO: a dual-clocked block RAM-based queue (write clock and read clock) that lets data move safely between clock domains, using internal synchronizers on the read/write address pointers.

Walkthrough

Setup, hold time, and metastability (0:00)

The lecture defines the setup and hold windows around a flip-flop's clock edge, explains that a violation can cause metastability - an unpredictable, temporarily unstable output - and notes that this is probabilistic and generally too fast to observe directly on an oscilloscope, referencing an external experiment that demonstrates it by deliberately shifting clock phase.

Building a synchronizer (4:08)

The fix for sampling an asynchronous or cross-domain signal is a chain of flip-flops (a synchronizer): each additional stage reduces the chance that metastability reaches the final output, at the cost of extra clock-cycle latency.

Clock domains and why crossing them is risky (6:11)

The lecture defines a clock domain and explains clock domain crossing - sampling a signal generated by one clock (say, an external 5 MHz SPI signal) with logic clocked by another (the 12 MHz system clock) - as a common source of hard-to-debug, intermittent failures, recommending a synchronizer at the receiving domain and, where possible, avoiding domain crossings altogether.

A better clock divider design (7:14)

The lecture revisits the series' earlier clock dividers, noting that generating a divided clock signal from flip-flop outputs effectively creates an unmanaged second clock domain. The improved design instead counts up to a parameterized maximum and asserts a one-cycle "tick" output, which downstream logic checks with a simple conditional inside its existing clocked always block - keeping the whole design in a single, well-behaved clock domain.

Introducing FIFOs for clock domain crossing (9:20)

A FIFO (first-in, first-out queue) is introduced as a memory-based way to pass data between a sender and receiver safely: elements are read in the order written, and code must track full/empty conditions to avoid reading from an empty FIFO or writing to a full one.

Asynchronous FIFOs and the challenge (11:24)

Using the iCE40's dual-clock block RAM (separate read and write clocks) and Clifford Cummings' well-known FIFO design as a reference, the lecture explains how synchronizer circuits on the internal read/write address pointers make the FIFO safe to use across two independent clock domains. The challenge is to implement this FIFO in Verilog and write a test bench proving it correctly handles full and empty conditions.

Before you watch

Complete Part 9 ("Phase-Locked Loop (PLL) and Glitches"); this lecture assumes familiarity with propagation delay and builds on that intuition for timing violations.
Recall the clock dividers built in Parts 4 and 6, since this lecture explains why that earlier approach should be improved.

Check your understanding

What is the difference between a setup time violation and a hold time violation?
Why does adding a second flip-flop to a synchronizer reduce the risk of metastability reaching the rest of the design?
Why does the lecture consider the series' earlier clock-divider designs bad practice, and how does the tick-based divider avoid that problem?
What conditions must a FIFO implementation guard against to avoid corrupting its data?
Why does an asynchronous FIFO need synchronizers on its internal read and write address pointers?

Vocabulary

setup time (noun): The minimum time a signal must stay stable before a clock edge for a flip-flop to capture it correctly.
Violating setup time can cause incorrect data capture.
hold time (noun): The minimum time a signal must stay stable after a clock edge for a flip-flop to capture it correctly.
A hold time violation happens if the signal changes too soon after the clock edge.
timing violation (noun): A case where a signal changes during a forbidden window around a clock edge.
A timing violation can leave a flip-flop's output unpredictable.
metastability (noun): An unstable state where a flip-flop's output sits between 0 and 1 before settling unpredictably.
Metastability can occur after a setup or hold time violation.
probabilistic (adjective): Governed by chance, with outcomes that vary and cannot be predicted exactly each time.
Metastability is a probabilistic failure, not a guaranteed one.
synchronizer (noun): A chain of flip-flops used to safely bring a signal into a new clock domain.
A synchronizer reduces the risk of metastability spreading further.
clock domain (noun): All the logic controlled by the same clock signal or a fixed divided version of it.
Crossing between clock domains risks introducing timing violations.
clock domain crossing (noun): Passing a signal from logic driven by one clock into logic driven by a different clock.
Clock domain crossing without a synchronizer can cause intermittent failures.
intermittent (adjective): Happening occasionally and unpredictably rather than every time.
Clock domain crossing bugs are often intermittent and hard to debug.
tick pulse (noun): A signal that stays high for exactly one clock cycle to mark a specific moment.
The improved divider produces a single-cycle tick pulse instead of a new clock.
FIFO (first in, first out) (noun): A queue where data is read out in the same order it was written in.
A FIFO safely passes data between two parts of a system.
asynchronous (adjective): Not controlled by or synchronized to a shared clock.
An asynchronous FIFO connects two independent clock domains.
address pointer (noun): A value tracking the next read or write position within a memory or buffer.
The FIFO's address pointers need their own synchronizers.
propagation delay (noun): The short time a signal takes to travel through a circuit.
This lecture builds on the intuition for propagation delay from the previous part.
deterministic (adjective): Always producing the same result from the same starting conditions.
Metastability is not deterministic, unlike most digital logic.
indeterminate (adjective): Not fixed or exactly known.
A flip-flop's output can stay unstable for an indeterminate time.
settle (verb): To finally reach a stable, unchanging value.
The output eventually settles to either 0 or 1.
oscilloscope (noun): An instrument that displays how an electrical signal changes over time.
Metastability is usually too fast to see directly on an oscilloscope.
phase (noun): The position of a repeating signal within its cycle, relative to another signal.
An experiment demonstrates metastability by shifting clock phase.
chain (verb): To connect several components one after another.
A synchronizer chains two or more flip-flops together.
cross-domain (adjective): Involving signals moving between two different clock domains.
A cross-domain signal needs a synchronizer before it is safe to use.
hard-to-debug (adjective): Difficult to find the cause of when something goes wrong.
Clock domain crossing bugs are often hard-to-debug and rare.
queue (noun): A line of items waiting to be processed in order.
A FIFO is a memory-based queue for passing data safely.
full condition (noun): The state where a buffer has no more room to store new data.
The code must check the full condition before writing to the FIFO.
empty condition (noun): The state where a buffer has no data left to read.
Reading during the empty condition would give invalid data.
conceptual (adjective): Related to general ideas rather than exact technical detail.
The lecture explains asynchronous FIFOs at a conceptual level.
preview (verb): To give a short early look at something that comes later.
The lecture previews building a RISC-V soft core next.

From the YouTube description

A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.

In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).

Previously, we showed how to use a phase-locked loop (PLL) to increase clock speed as well as introduced the concept of glitches. In this episode, we examine how setup and hold time violations can cause metastability in flip-flops.

The solution to the challenge at the end of the episode can be found here: https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-10-metastability-and-fifo/74884ed134474e008a1e444ea9dacb0f

All code examples and solutions for this series can be found here: https://github.com/ShawnHymel/introduction-to-fpga

Colin O’Flynn’s metastability experiment: https://colinoflynn.com/2020/12/experimenting-with-metastability-and-multiple-clocks-on-fpgas

Better clock divider example: https://github.com/ShawnHymel/introduction-to-fpga/tree/main/10-metastability/example-02-better-clock-divider

Better button debounce design: https://github.com/ShawnHymel/introduction-to-fpga/tree/main/10-metastability/example-03-better-debouncer

Clifford Cummings’s FIFO paper: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf

A flip-flop requires the input signal to be steady for some time before the clock edge (setup time) and remain steady for some time after the clock edge (hold time). If the input signal transitions during the setup or hold windows, then it is considered a timing violation. This could potentially cause metastability on the flip-flop, where the output remains in an unknown state for some indeterminate amount of time.

Normally, the metastable output will settle on logic high or logic low quickly (within a few nanoseconds), but it is not guaranteed. Metastable events can cause potentially catastrophic failures in a design and can be very difficult to track down due to their probabilistic nature.

The standard fix to mitigate the likelihood and impact of metastability is to use a synchronizer circuit, which consists of 2 or more flip-flops chained together. The input of one flip-flop samples the output of another. Note that this introduces an extra clock cycle of delay for each flip-flop you put in the chain.

A first-in, first-out (FIFO) system is one way to pass data from one class domain to another. Elements are read from the FIFO in the order in which they were written. We can use dual-port block RAM to construct a FIFO in our iCE40. Your challenge is to implement Clifford Cummings’s FIFO design and test it via simulation.

Product Links:
https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/ICE40HX1K-STICK-EVN/4289604

Related Videos:
https://www.youtube.com/watch?v=z8Oldd-nrfs
https://www.youtube.com/watch?v=5kNXX67mchE
https://www.youtube.com/watch?v=iwcxLQ6AB88

Related Project Links:
https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-10-metastability-and-fifo/74884ed134474e008a1e444ea9dacb0f

Related Articles:
https://www.digikey.com/en/pdf/r/renesas-electronics-america/powering-fpga-applications
https://www.digikey.com/en/videos/d/dsp/edge-machine-deep-learning-on-fpga

Learn more:
Maker.io - https://www.digikey.com/en/maker
Digi-Key’s Blog – TheCircuit https://www.digikey.com/en/blog
Connect with Digi-Key on Facebook https://www.facebook.com/digikey.electronics/
And follow us on Twitter https://twitter.com/digikey

← Part 9: Phase-Locked Loop (PLL) and Glitches · Part 11: RISC-V Softcore Processor →