Part 4: Clocks and Procedural Assignments

What this lecture covers

Having used only continuous assignments so far, this lecture introduces sequential logic: circuits whose output depends on a clock signal, not just current inputs. It answers how the D flip-flop inside each iCE40 logic cell stores one bit between clock edges, and how Verilog's always blocks and procedural (<=) assignments describe that behavior.

By the end you can explain what a D flip-flop, reset, and enable line do, and you've built and tested a 4-bit counter that increments on a button press and resets on another, displaying its value in binary on the LEDs. The episode sets up a challenge to drive the same counter from the board's 12 MHz oscillator instead of a button.

Key ideas

• D flip-flop: stores one bit, sampling its input only on a clock edge (rising edge by default); it holds its output between edges.
• Reset and enable lines: reset asynchronously forces the output low regardless of the clock; enable, when low, freezes the output even as the clock toggles.
• reg keyword: declares that a signal is driven from a flip-flop inside a procedural block, rather than wired directly with assign.
• always block: describes logic that executes sequentially, similar to a programming language, triggered by a sensitivity list of signal edges (for example posedge clock or posedge reset).
• Non-blocking assignment (<=): used inside always blocks to load a new value into a register on a clock edge, distinct from the continuous assign used for wires.
• Synthesizable arithmetic: Verilog's + operator can be used directly; the synthesis tool generates whatever adder circuitry is needed, without the designer building it from gates.
• Button debounce: mechanical buttons can register multiple transitions per press; the lecture notes this causes skipped or repeated counts and defers a proper fix to a later episode.

Walkthrough

The D flip-flop and its control lines (0:23)

Using the iCE40 datasheet's logic cell diagram, the lecture explains that each cell contains a D flip-flop alongside its lookup table, with clock, reset, and enable inputs, and a multiplexer that can bypass the flip-flop entirely. It walks through the flip-flop's timing behavior: sampling the input only on a rising clock edge, and how reset and enable modify that behavior.

Designing the 4-bit counter (2:30)

The lecture sketches a 4-bit counter built from flip-flops and adder logic, using a timing diagram to show the count going from an unknown state at power-up, to a known 0 after a reset pulse, and incrementing by 1 on each clock edge until it rolls over from 15 back to 0. Counters are framed as the basis for timers and pulse-width modulation.

Setting up the button-counter project (5:03)

A new project folder and .pcf file define a 4-bit LED bus and two button inputs as vectors, following the same pattern as earlier episodes.

always blocks and procedural assignment (8:01)

The Verilog module declares the LED bus as reg, inverts the two buttons into reset and clock nets with continuous assignments, then defines an always @(posedge clock or posedge reset) block. Inside, an if (reset) branch loads all zeros into the LED bus, and an else branch increments it, using non-blocking assignment (<=) because the value is stored in a register rather than wired continuously.

Synthesizable addition (14:34)

The lecture points out that writing led <= led + 1 is enough for the synthesis tool to build whatever adder circuitry is required - it does not need to be hand-designed as in the previous episode's full adder challenge.

Testing and the clock divider challenge (16:32)

After building and uploading, the counter increments each time one button is pressed and resets with the other, with visible skips from button bounce. The lecture identifies the iCEstick's 12 MHz oscillator on physical pin 21 as a better clock source and sets the challenge: build a clock divider that turns it into a 1 Hz signal to drive the counter automatically.

Before you watch

• Complete Part 3 ("Getting Started with Verilog"), since this lecture builds directly on continuous assignments and vectors covered there.
• Review the full adder challenge from Part 3; this lecture references it when discussing synthesizable addition.

Check your understanding

1. What is the difference between how a D flip-flop's reset and enable lines affect its output?
2. Why does the LED bus need to be declared as reg instead of wire in this design?
3. What triggers the always block in the counter design, and what does each branch of the if/else do?
4. Why is <= used inside the always block instead of the assign keyword?
5. What is the challenge set at the end of the lecture, and what hardware resource does it point you toward?