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FPGA & Verilog Design · Lecture 4 of 12 · 18:09

Part 4: Clocks and Procedural Assignments

Study guide

What this lecture covers

Having used only continuous assignments so far, this lecture introduces sequential logic: circuits whose output depends on a clock signal, not just current inputs. It answers how the D flip-flop inside each iCE40 logic cell stores one bit between clock edges, and how Verilog's always blocks and procedural (<=) assignments describe that behavior.

By the end you can explain what a D flip-flop, reset, and enable line do, and you've built and tested a 4-bit counter that increments on a button press and resets on another, displaying its value in binary on the LEDs. The episode sets up a challenge to drive the same counter from the board's 12 MHz oscillator instead of a button.

Key ideas

D flip-flop: stores one bit, sampling its input only on a clock edge (rising edge by default); it holds its output between edges.
Reset and enable lines: reset asynchronously forces the output low regardless of the clock; enable, when low, freezes the output even as the clock toggles.
reg keyword: declares that a signal is driven from a flip-flop inside a procedural block, rather than wired directly with assign.
always block: describes logic that executes sequentially, similar to a programming language, triggered by a sensitivity list of signal edges (for example posedge clock or posedge reset).
Non-blocking assignment (<=): used inside always blocks to load a new value into a register on a clock edge, distinct from the continuous assign used for wires.
Synthesizable arithmetic: Verilog's + operator can be used directly; the synthesis tool generates whatever adder circuitry is needed, without the designer building it from gates.
Button debounce: mechanical buttons can register multiple transitions per press; the lecture notes this causes skipped or repeated counts and defers a proper fix to a later episode.

Walkthrough

The D flip-flop and its control lines (0:23)

Using the iCE40 datasheet's logic cell diagram, the lecture explains that each cell contains a D flip-flop alongside its lookup table, with clock, reset, and enable inputs, and a multiplexer that can bypass the flip-flop entirely. It walks through the flip-flop's timing behavior: sampling the input only on a rising clock edge, and how reset and enable modify that behavior.

Designing the 4-bit counter (2:30)

The lecture sketches a 4-bit counter built from flip-flops and adder logic, using a timing diagram to show the count going from an unknown state at power-up, to a known 0 after a reset pulse, and incrementing by 1 on each clock edge until it rolls over from 15 back to 0. Counters are framed as the basis for timers and pulse-width modulation.

Setting up the button-counter project (5:03)

A new project folder and .pcf file define a 4-bit LED bus and two button inputs as vectors, following the same pattern as earlier episodes.

`always` blocks and procedural assignment (8:01)

The Verilog module declares the LED bus as reg, inverts the two buttons into reset and clock nets with continuous assignments, then defines an always @(posedge clock or posedge reset) block. Inside, an if (reset) branch loads all zeros into the LED bus, and an else branch increments it, using non-blocking assignment (<=) because the value is stored in a register rather than wired continuously.

Synthesizable addition (14:34)

The lecture points out that writing led <= led + 1 is enough for the synthesis tool to build whatever adder circuitry is required - it does not need to be hand-designed as in the previous episode's full adder challenge.

Testing and the clock divider challenge (16:32)

After building and uploading, the counter increments each time one button is pressed and resets with the other, with visible skips from button bounce. The lecture identifies the iCEstick's 12 MHz oscillator on physical pin 21 as a better clock source and sets the challenge: build a clock divider that turns it into a 1 Hz signal to drive the counter automatically.

Before you watch

Complete Part 3 ("Getting Started with Verilog"), since this lecture builds directly on continuous assignments and vectors covered there.
Review the full adder challenge from Part 3; this lecture references it when discussing synthesizable addition.

Check your understanding

What is the difference between how a D flip-flop's reset and enable lines affect its output?
Why does the LED bus need to be declared as reg instead of wire in this design?
What triggers the always block in the counter design, and what does each branch of the if/else do?
Why is <= used inside the always block instead of the assign keyword?
What is the challenge set at the end of the lecture, and what hardware resource does it point you toward?

Vocabulary

sequential logic (noun): A circuit type whose output depends on stored history, not just current inputs.
Sequential logic needs a clock signal to control state changes.
D flip-flop (noun): A memory element that stores one bit, updating only on a clock edge.
Each logic cell contains a D flip-flop next to its lookup table.
rising edge (noun): The exact moment a clock signal changes from low to high.
The flip-flop samples its input only on the rising edge.
reset line (noun): A signal that forces a circuit into a known starting state.
The reset line clears the counter back to zero.
enable line (noun): A signal that allows or blocks a circuit from updating.
When the enable line is low, the flip-flop's output stays frozen.
reg (noun): A Verilog keyword marking a signal that is driven inside a procedural block, like an always block.
The LED bus is declared as reg because it's updated in an always block.
always block (noun): A Verilog block that runs whenever its listed trigger signals occur.
The counter logic sits inside an always block.
sensitivity list (noun): The set of signals that trigger an always block to run again.
The sensitivity list includes posedge clock and posedge reset.
non-blocking assignment (noun): A Verilog assignment (<=) that updates registers using old values, applied all at once.
Non-blocking assignment is used to increment the counter register.
rollover (noun): When a counter reaches its maximum value and wraps back to its minimum.
The counter rolls over from 15 back to 0.
pulse-width modulation (noun): A technique that varies a signal's on/off timing to control something like brightness or speed.
Counters form the basis for pulse-width modulation circuits.
button bounce (noun): Rapid, unwanted electrical fluctuations that happen when a mechanical button is pressed.
Button bounce causes the counter to skip or repeat values.
oscillator (noun): A component that produces a repeating electrical signal at a fixed frequency.
The 12 MHz oscillator provides a stable clock source.
clock divider (noun): A circuit that reduces a fast clock signal into a slower one.
A clock divider turns the fast oscillator into a visible 1 Hz signal.
continuous assignment (noun): A Verilog statement (using assign) that constantly drives a wire's value.
Earlier lectures used only continuous assignments, not always blocks.
procedural assignment (noun): An assignment made inside an always block rather than with a continuous assign statement.
Procedural assignment lets the counter update on each clock edge.
vector (noun): A group of related signal bits treated as one multi-bit value.
The button inputs are declared as vectors in the pcf file.
multiplexer (noun): A circuit that selects one of several input signals to pass through.
A multiplexer inside the logic cell can bypass the flip-flop entirely.
timing diagram (noun): A drawing that shows how signals change over time.
A timing diagram shows the counter's value after each clock edge.
power-up (noun): The moment a circuit first turns on.
The counter's value is unknown at power-up until reset is applied.
invert (verb): To flip a signal's value from high to low or low to high.
The buttons are inverted into active-high reset and clock signals.
increment (verb): To increase a value by a fixed amount, usually one.
The counter increments by one on every clock edge.
adder (noun): A circuit that produces the sum of two binary numbers.
The synthesis tool builds the adder needed for led <= led + 1.
full adder (noun): A circuit that adds two bits together along with a carry-in bit.
The full adder challenge from an earlier lecture required hand design.
hand-design (verb): To build something manually rather than letting a tool generate it.
This counter avoids the need to hand-design an adder from gates.
defer (verb): To put off doing something until a later time.
The lecture defers a proper fix for button bounce to a later episode.
physical pin (noun): An actual metal connection point on a chip package.
The 12 MHz oscillator is available on physical pin 21.
framed as (phrase): Presented or described in a certain way.
Counters are framed as the basis for timers and PWM circuits.

Chapters

0:00 Introduction
0:23 DFlip Flop
1:08 Simple DFlip Flop
2:30 Creating a 4Bit Counter
3:33 Timing Diagram
5:03 Creating the Project
6:15 Creating the Verilog File
8:01 Continuous Assignments
12:50 End Else
14:34 Addition
16:32 Demonstration
17:44 Outro

From the YouTube description

A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.

In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).

Previously, we showed how to use continuous assignment statements to create custom digital circuits with logic gates using Verilog (https://youtu.be/A4VfBoP4Hdk). In this episode, we demonstrate how to use procedural assignments to create sequential hardware logic.

The solution to the challenge at the end of the episode can be found here: https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-4-clocks-and-procedural-assignments/356e12284daf48b5bd9b80af8a6ac5b8

All code examples and solutions for this series can be found here: https://github.com/ShawnHymel/introduction-to-fpga

We start by showing how the D flip-flop in an FPGA logic cell can be used to store a 1-bit value for one or (potentially) more clock cycles. Multiple D flip-flops can be combined with combinational logic gates to create hardware circuits that operate sequentially. We can control this sequential logic through Verilog blocks known as “procedural assignment statements.”

Next, we demonstrate a procedural assignment statement by constructing a simple 4-bit counter inside of an “always block.” Each time a button is pressed, the value increments by 1. The counter value is shown on the LEDs (in binary).

Note that you will likely experience button bounce that we have not accounted for in the demonstration. As a result, the counter will likely skip values each button press. You would need to implement button debounce circuitry (either in hardware or in HDL) to correct for this behavior. We will cover button debounce in a future episode.

Your challenge is to create a clock divider for the onboard 12 MHz oscillator (assuming you are using the iCEstick, the 12 MHz oscillator is connected to pin 21). The clock should be divided to 1 Hz, and this new clock signal should run the counter shown in the video. The new counter should increment on its own once per second.

Product Links:
https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/ICE40HX1K-STICK-EVN/4289604

Related Videos:
https://www.youtube.com/watch?v=z8Oldd-nrfs
https://www.youtube.com/watch?v=5kNXX67mchE
https://www.youtube.com/watch?v=iwcxLQ6AB88

Related Project Links:
https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-4-clocks-and-procedural-assignments/356e12284daf48b5bd9b80af8a6ac5b8

Related Articles:
https://www.digikey.com/en/pdf/r/renesas-electronics-america/powering-fpga-applications
https://www.digikey.com/en/videos/d/dsp/edge-machine-deep-learning-on-fpga

Learn more:
Maker.io - https://www.digikey.com/en/maker
Digi-Key’s Blog – TheCircuit https://www.digikey.com/en/blog
Connect with Digi-Key on Facebook https://www.facebook.com/digikey.electronics/
And follow us on Twitter https://twitter.com/digikey

← Part 3: Getting Started with Verilog · Part 5: Finite State Machines →