Seyed Masoud Hosseini · Overview · Study log · Weekly summaries · Ideas · Search · Transcript · RSS feed

FPGA & Verilog Design · Lecture 3 of 12 · 20:43

Part 3: Getting Started with Verilog

Introduction to FPGA Part 3 - Getting Started with Verilog | Digi-Key Electronics on YouTube

Study guide

What this lecture covers

With the toolchain installed, this lecture writes the first real Verilog designs: a two-input AND gate driven by pushbuttons, then a small circuit that drives three LEDs from two buttons using vectors. It answers how a .pcf file and a Verilog module work together, and what actually happens inside the FPGA when combinational logic is synthesized.

By the end you can wire buttons and LEDs to the iCEstick's Pmod header, write a module with continuous assignments, and explain why a synthesized AND gate is really a 16-entry lookup table indexed by its inputs rather than a literal logic gate. The episode ends with a challenge to build a 1-bit full adder.

Key ideas

  • Pmod connector: a standard header (power, ground, I/O pins) used throughout the series to attach buttons, LEDs, and other breakout boards to the iCEstick.
  • Internal pull-ups: the .pcf file can enable an FPGA pin's internal pull-up resistor (-pullup yes) so buttons don't need external resistors; pressing a button pulls the line low.
  • Module and continuous assignment: a Verilog module defines a hardware block with named inputs/outputs; an assign statement wires those signals together permanently, with no clock or execution order involved.
  • Vectors: grouping related signals with bracket notation (for example [1:0]), similar to an array, instead of naming each bit separately.
  • Replication: the {n{signal}} syntax copies a signal onto multiple outputs, letting one wire drive several LEDs at once.
  • Lookup table (LUT): a 4-input logic cell on the iCE40 is implemented as a 16-entry, 1-bit memory; the inputs act as an address, and synthesis writes the correct truth table into that memory rather than building discrete logic gates.

Walkthrough

Pmod connector and pull-ups (0:26)

The lecture describes the Pmod header's pinout on the iCEstick and wires three buttons to it. It explains that internal pull-up resistors, enabled per pin in the .pcf file, remove the need for external pull-up resistors.

Building the AND gate circuit (1:36)

Starting from a truth table (output high only when both buttons are pressed), the lecture creates the .pcf file mapping led0, pmod0, and pmod1 to physical pins, then writes a Verilog module with two inputs and one output. A single continuous assignment ANDs the inverted button lines together (buttons are active low) and drives the LED - described as equivalent to wiring the circuit on a breadboard rather than running code.

Building and testing on hardware (10:30)

After apio init --board icestick, apio build, and apio upload, pressing both buttons together lights the LED while pressing either one alone does not, confirming the design works.

How lookup tables implement logic (11:06)

Using the iCE40 datasheet's logic cell diagram, the lecture explains that each cell's 4-input lookup table is not a collection of gates but a 16-entry memory. During configuration, the truth table's output column is written into that memory, and the input lines act as an address that selects which bit to output - similar to a 16-to-1 multiplexer.

Vectors and replication (12:37)

A second example drives three LEDs from two buttons: pressing the first button lights two LEDs, and pressing both lights a third. The lecture introduces vector declarations (pmod[1:0], leds[4:0]), the wire keyword for naming internal nets, and the replication operator ({2{...}}) to duplicate one signal across two output pins.

Full adder challenge (19:03)

The lecture points to a Verilog quick reference card and sets a challenge: implement a 1-bit full adder (sum and carry-out from three input bits) using the same continuous-assignment approach, demonstrating a working solution on the iCEstick before closing.

Before you watch

  • Complete Part 2 ("Getting Started with Yosys, IceStorm, and Apio") so the toolchain and apio build/apio upload workflow are already set up.
  • Basic familiarity with Boolean logic and truth tables (AND, NOT) will make the circuit examples easier to follow.

Check your understanding

  1. Why does the AND gate design invert the button inputs before ANDing them together?
  2. What does a .pcf file do, and how does it relate to the Verilog module's input and output names?
  3. How does a 4-input lookup table implement a truth table without using discrete logic gates?
  4. What is the difference between a scalar net and a vector in Verilog, based on the examples shown?
  5. What does the replication operator do, and where was it used in the three-LED example?

Vocabulary

connector (noun)
A physical socket used to attach external components like buttons or LEDs.
The Pmod connector attaches buttons to the board.
pull-up resistor (noun)
A resistor that holds a signal at a high level until something pulls it low.
The internal pull-up resistor removes the need for an external one.
active low (adjective)
Describes a signal that is considered 'on' or 'true' when it is at a low voltage.
The buttons are active low, so pressing them pulls the line to zero.
module (noun)
A Verilog block that defines a hardware component with named inputs and outputs.
The Verilog module has two inputs and one output.
continuous assignment (noun)
A permanent connection in Verilog made with the assign keyword, always active.
A continuous assignment wires the AND result directly to the LED.
vector (noun)
A group of related signal bits declared together, like an array.
The vector pmod[1:0] groups two button signals together.
wire (noun)
A Verilog data type used to name and connect internal signals.
The wire keyword names an internal net between components.
replication operator (noun)
Verilog syntax that copies a signal onto multiple output bits at once.
The replication operator drives two LEDs from one signal.
lookup table (LUT) (noun)
A small memory that stores the output for every possible input combination.
A four-input lookup table implements the AND gate's logic.
multiplexer (noun)
A circuit that selects one of several inputs to output based on a control signal.
The lookup table behaves like a sixteen-to-one multiplexer.
full adder (noun)
A circuit that adds three input bits and produces a sum and a carry-out.
The challenge asks you to build a one-bit full adder.
carry-out (noun)
The extra bit produced when an addition's result is too large to fit in one bit.
The full adder outputs a sum and a carry-out.
pinout (noun)
A diagram or list showing what each physical pin on a connector is used for.
The lecture describes the Pmod header's pinout.
breakout board (noun)
A small board that exposes a chip's pins in an easier-to-use connector format.
Breakout boards can attach extra components to the iCEstick.
net (noun)
A named electrical connection between components in a circuit.
The wire keyword names an internal net in the design.
truth table (noun)
A table listing every input combination and its resulting output.
The design starts from a truth table for the AND gate.
configuration (noun)
The process of setting up a device's internal structure to perform a specific function.
The truth table is written into the lookup table during configuration.
address (noun)
A value used to select a specific location in a memory.
The input lines act as an address into the lookup table's memory.
scalar net (phrase)
A single-bit signal, as opposed to a multi-bit vector.
A scalar net carries only one bit of information.
quick reference card (phrase)
A short document summarizing key syntax or commands for fast lookup.
The lecture points to a Verilog quick reference card for the challenge.
demonstrate (verb)
To show something working in practice.
The challenge asks you to demonstrate a working solution on the iCEstick.
combinational logic (phrase)
Logic whose output depends only on its current inputs, with no memory of the past.
The AND gate circuit is an example of combinational logic.
duplicate (verb)
To make an extra copy of something.
The replication operator duplicates one signal onto two pins.
internal (adjective)
Located or happening inside a system rather than outside it.
The internal pull-up resistor is built into the FPGA pin.
breadboard (noun)
A board used to build and test electronic circuits without soldering.
The design is compared to wiring a circuit on a breadboard.

Chapters

From the YouTube description

In this tutorial, we demonstrate how to use continuous assignment statements in Verilog to construct digital logic circuits on an FPGA.

A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.

In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).

Previously, we showed how to install apio and the open-source toolchain required to work with Lattice iCE40 FPGAs (https://youtu.be/gtkQ84Euyww). In this episode, we demonstrate how to write simple continuous assignment statements in Verilog to create digital logic circuits.

Wikipedia article on adders: https://en.wikipedia.org/wiki/Adder_(electronics)
The solution to the challenge at the end of the episode can be found here: https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-3-getting-started-with-verilog/9d9dbff29a4b45728521b2664bbd1df4

All code examples and solutions for this series can be found here: https://github.com/ShawnHymel/introduction-to-fpga

We start by showing how to define pins using a physical constraints file (.pcf), which maps Verilog I/O signal names to physical pin numbers on the FPGA package. Refer to the following documents to see the pinout on the iCE40HX1K and how it’s connected on the iCEstick:

- iCE40 LP/HX Datasheet
- iCEstick Evaluation Kit User’s Guide

From there, we show how lookup tables are used to construct digital circuits inside the FPGA. We design a very simple digital circuit (a simple AND gate with pushbutton inputs) in Verilog, synthesize it, and upload it to the iCEstick.

Next, we demonstrate how vectors work in Verilog (as a bus of wires) and how to branch wires using the replication operation.

Verilog Quick Reference Card: http://www.ee.ic.ac.uk/pcheung/teaching/ee2_digital/Verilog%20Quick%20Reference%20Card%20v2_0.pdf

Your challenge is to create a 1-bit full adder as shown in this Wikipedia article.

Product Links:
https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/ICE40HX1K-STICK-EVN/4289604
Related Videos:
https://www.youtube.com/watch?v=z8Oldd-nrfs
https://www.youtube.com/watch?v=5kNXX67mchE
https://www.youtube.com/watch?v=iwcxLQ6AB88
Related Project Links:
https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-3-getting-started-with-verilog/9d9dbff29a4b45728521b2664bbd1df4
Related Articles:
https://www.digikey.com/en/pdf/r/renesas-electronics-america/powering-fpga-applications
https://www.digikey.com/en/videos/d/dsp/edge-machine-deep-learning-on-fpga

Learn more:
Maker.io - https://www.digikey.com/en/maker
Digi-Key’s Blog – TheCircuit https://www.digikey.com/en/blog
Connect with Digi-Key on Facebook https://www.facebook.com/digikey.electronics/
And follow us on Twitter https://twitter.com/digikey

← Part 2: Getting Started with Yosys, IceStorm, and Apio · Part 4: Clocks and Procedural Assignments →