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FPGA & Verilog Design · Lecture 9 of 12 · 23:28

Part 9: Phase-Locked Loop (PLL) and Glitches

Introduction to FPGA Part 9 - Phase-Locked Loop (PLL) and Glitches | Digi-Key Electronics on YouTube

Study guide

What this lecture covers

This lecture answers two related questions: how do you get a faster clock than the iCEstick's 12 MHz oscillator, and what goes wrong in digital logic once clock speeds increase? It configures the iCE40's on-chip phase-locked loop (PLL) as a clock multiplier producing 120 MHz, verifies the result on an oscilloscope, then uses a simulated four-bit ripple counter to show how propagation delay causes glitches - momentary incorrect values - that become a real problem only at high clock speeds.

By the end you can calculate PLL divider settings with the icepll tool, instantiate the SB_PLL40_CORE primitive in Verilog, and explain why a ripple counter's un-registered output can briefly show wrong values, and why that usually doesn't matter for a registered output at normal clock speeds.

Key ideas

  • Phase-locked loop (PLL): a circuit that produces an output whose frequency and phase are locked to a reference signal, built from a voltage-controlled oscillator, phase detector, and low-pass filter.
  • Clock multiplication: inserting a divider between the oscillator and phase detector forces the VCO to run at a multiple of the reference frequency, letting a PLL turn a slow reference clock into a much faster output clock.
  • icepll tool: calculates the reference, feedback, and VCO dividers needed to hit a target output frequency from a given input frequency, sparing you the manual math from the Lattice PLL design guide.
  • SB_PLL40_CORE: the iCE40-specific primitive used to instantiate the on-chip PLL in Verilog, configured with the divider values from icepll, a simple feedback path, and the GENCLK output select for no phase shift.
  • Propagation delay: the small but nonzero time it takes a signal change to move through a wire or lookup table, which becomes significant relative to a clock period as clock speed increases.
  • Glitch: a brief, incorrect intermediate value that appears while a multi-bit signal (like a ripple counter's un-registered output) settles, caused by different bits updating after different propagation delays.
  • Registered output safety: because the counter's actual output is captured on a clock edge, glitches on the combinational path usually don't matter at normal clock speeds - only if the clock is fast enough that a glitch occurs right at the sampling edge does it become a real bug.

Walkthrough

What a PLL does (0:29)

The lecture explains the PLL's components - VCO, phase detector, low-pass filter - and how adding a divider in the feedback path turns the circuit into a clock multiplier, using a 36 MHz-to-12 MHz example to illustrate the idea.

Calculating PLL settings with icepll (1:40)

Referencing the Lattice PLL design and usage guide's constraints (reference clock 10-133 MHz, VCO output 533-1066 MHz, final output 16-275 MHz), the lecture runs icepll -i 12 -o 120 to get the reference, feedback, and VCO divider values (and filter range) needed to turn the iCEstick's 12 MHz clock into 120 MHz.

Implementing the PLL in Verilog (6:03)

The lecture instantiates SB_PLL40_CORE with the calculated divider parameters, a simple feedback path, GENCLK output select, and an always-enabled active-low reset, connecting the reference clock to pin 21 and routing the multiplied output to a Pmod pin for measurement. Uploading the design and probing the output pin with an oscilloscope confirms a 120 MHz signal, though the waveform is visibly distorted at that frequency.

Propagation delay (10:16)

The lecture introduces propagation delay - the time for a signal change to appear at a gate or lookup table's output - and notes that the iCE40 datasheet only specifies pin-to-pin delay through a LUT, leaving internal delays for the place-and-route tool to manage.

Ripple counter and glitches (12:09)

Using a four-bit ripple counter built from half adders with simulated one-nanosecond gate delays in a test bench, the lecture shows that each bit updates sequentially rather than all at once, so the un-registered sum output briefly passes through incorrect intermediate values before settling.

Observing glitches in GTKWave (19:08)

Simulation waveforms show the un-registered output briefly reading 0 when it should read 2, and similar momentary errors elsewhere, while the registered count value updates correctly each clock cycle. The lecture explains that this only becomes a real bug if the clock is fast enough that a sampling edge lands during a glitch, and closes with a challenge to design a counter that reduces or eliminates this glitching.

Before you watch

  • Complete Part 8 ("Memory and Block RAM"); this lecture assumes familiarity with writing test benches and using GTKWave from earlier episodes.
  • Recall the full adder / half adder logic from Part 3, since the ripple counter example is built from half adders.

Check your understanding

  1. How does adding a divider in a PLL's feedback path turn it into a clock multiplier?
  2. What values does icepll calculate, and why is manual computation from the datasheet impractical?
  3. Why does the iCE40 datasheet only specify propagation delay from pin to pin through a lookup table?
  4. In the ripple counter example, why does the un-registered out value glitch but the registered count value normally does not?
  5. Under what condition would a glitch in the ripple counter actually corrupt the counter's stored value?

Vocabulary

phase-locked loop (PLL) (noun)
A circuit that produces an output signal locked in frequency and phase to a reference signal.
The PLL multiplies the oscillator's clock up to 120 MHz.
clock multiplier (noun)
A circuit that turns a slower clock signal into a faster one.
Adding a divider in the feedback path makes the PLL act as a clock multiplier.
voltage-controlled oscillator (noun)
A circuit that generates a signal whose frequency changes based on an input voltage.
The PLL contains a voltage-controlled oscillator inside its feedback loop.
phase detector (noun)
A circuit that compares the timing of two signals and outputs their difference.
The phase detector keeps the PLL's output aligned with the reference clock.
low-pass filter (noun)
A circuit that lets slow signal changes through while blocking fast ones.
A low-pass filter smooths the phase detector's output.
primitive (noun)
A built-in hardware component provided directly by the chip vendor.
SB_PLL40_CORE is the iCE40's built-in PLL primitive.
propagation delay (noun)
The time it takes a signal change to travel through a circuit element.
Propagation delay through the lookup table becomes significant at high speed.
ripple counter (noun)
A counter where each bit's change triggers the next bit, causing delays to build up.
The ripple counter's bits don't all update at exactly the same instant.
glitch (noun)
A brief, incorrect signal value that appears while a circuit settles.
A glitch briefly shows the wrong count before the correct value appears.
half adder (noun)
A simple circuit that adds two single bits and produces a sum and carry.
The ripple counter is built from a chain of half adders.
settle (verb)
To reach a final, stable value after some brief fluctuation.
The output takes a moment to settle after the input changes.
sampling edge (noun)
The specific clock edge moment when a flip-flop reads its input.
A glitch only matters if it lands right at the sampling edge.
reference signal (noun)
The steady signal that another circuit is adjusted to match.
The PLL's output is locked in phase to the reference signal.
feedback path (noun)
A route that sends part of a circuit's output back to its own input.
A divider is inserted into the feedback path to multiply the clock.
frequency (noun)
How many times a repeating signal cycles per second.
The PLL raises the clock frequency to 120 MHz.
spare [someone] [something] (phrase)
To save someone from doing extra, tedious work.
The icepll tool spares you the manual math for divider settings.
probe (verb)
To touch a test instrument to a circuit point to measure a signal.
Probing the output pin with an oscilloscope confirms 120 MHz.
distorted (adjective)
Changed from its normal, clean shape.
The waveform looks visibly distorted at 120 MHz.
significant (adjective)
Large enough to matter or have a noticeable effect.
Propagation delay becomes significant relative to the clock period.
un-registered (adjective)
Not stored in a flip-flop, so it can change freely between clock edges.
The ripple counter's un-registered output can briefly show wrong values.
sequentially (adverb)
One after another, in order.
Each bit of the ripple counter updates sequentially.
intermediate value (noun)
A temporary value that appears between a starting value and a final value.
The signal passes through an incorrect intermediate value before settling.
corrupt (verb)
To damage data so it becomes wrong or unusable.
A mistimed glitch could corrupt the counter's stored value.
manual math (noun)
Calculations done by hand instead of by a tool.
icepll avoids the manual math needed to set PLL dividers.
specify (verb)
To state something clearly and exactly.
The datasheet only specifies pin-to-pin delay through a lookup table.

Chapters

From the YouTube description

A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.

In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).

Previously, we showed how to use block RAM to store data in an FPGA (https://youtu.be/CJVMFjonx_s). In this episode, we will see how to use a phase-locked loop (PLL) to increase the clock speed as well as discuss how glitches can occur.

The solution to the challenge at the end of the episode can be found here: https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-9-phaselocked-loop-pll-and-glitches/2028ce62001b4cb69335f48e127fa366

All code examples and solutions for this series can be found here: https://github.com/ShawnHymel/introduction-to-fpga

A phase-locked loop (PLL) is a digital circuit that produces a repeating pattern (e.g. sinewave, square wave) with a frequency and phase matched to the input reference signal. PLLs have many uses, including demodulation and clock multipliers.

The iCE40 has a built-in PLL circuit that can be configured as a clock multiplier. The feedback mechanism contains a clock divider so that the voltage controlled oscillator (VCO) must output a clock that, when divided, matches the reference signal.

In the video, we use the icepll tool to calculate the parameters necessary to produce a 120 MHz clock from the 12 MHz reference signal. We then output that faster clock to a pin and measure it with an oscilloscope.

We introduce the concept of glitches, which are spurious transitions that may be incorrect data. For example, a simple adder circuit can introduce glitches due to gate delays. The carry bit takes some time to move through a simple ripple-carry adder/counter, and glitches can be seen on the output before the value is registered in flip-flops.

We conclude with a challenge: can you think of another way to design a counter that reduces or eliminates glitches?

Product Links:
https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/ICE40HX1K-STICK-EVN/4289604

Related Videos:
https://www.youtube.com/watch?v=z8Oldd-nrfs
https://www.youtube.com/watch?v=5kNXX67mchE
https://www.youtube.com/watch?v=iwcxLQ6AB88

Related Project Links:
https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-9-phaselocked-loop-pll-and-glitches/2028ce62001b4cb69335f48e127fa366

Related Articles:
https://www.digikey.com/en/pdf/r/renesas-electronics-america/powering-fpga-applications
https://www.digikey.com/en/videos/d/dsp/edge-machine-deep-learning-on-fpga

Learn more:
Maker.io - https://www.digikey.com/en/maker
Digi-Key’s Blog – TheCircuit https://www.digikey.com/en/blog
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And follow us on Twitter https://twitter.com/digikey

← Part 8: Memory and Block RAM · Part 10: Metastability and Clock Domain Crossing →