Part 8: Memory and Block RAM

What this lecture covers

This lecture answers how to store more than a few bits of data on an FPGA. It contrasts using individual flip-flops or lookup tables (distributed RAM) with the iCE40's dedicated embedded block RAM (EBR), then writes plain Verilog that lets the synthesis tool infer a small dual-port memory rather than instantiating it with vendor-specific system functions.

By the end you can declare a memory array in Verilog, write and read it through an always block, check how many block RAM resources a design uses via the device utilization report, test the memory with a test bench and GTKWave, and initialize memory contents from a text file at configuration time - including building simple read-only memory. The episode sets up a challenge to build an 8-step LED sequencer using memory, a clock divider, and a button debouncer together.

Key ideas

• Distributed RAM: small amounts of storage can be built from lookup tables when block RAM isn't needed, at the synthesis tool's discretion.
• Embedded block RAM (EBR): dedicated on-chip memory blocks (4Kb each on the iCE40HX1K, 16 blocks total) configurable as single-port, dual-port, or FIFO memory with different width/depth combinations.
• Minimum block allocation: declaring even a tiny memory (like 16 x 8 bits) still consumes one entire 4Kb block; you can't share the rest of that block for something else.
• Inferred memory: writing a registered array (reg [7:0] mem [0:15]) and reading/writing it inside a clocked always block lets the synthesis tool recognize and map it onto block RAM automatically.
• Read-before-write: on the iCE40, reading and writing the same address in the same clock cycle returns the old value before the new one is stored; other FPGAs may behave differently.
• Memory initialization file: $readmemh inside a synthesizable initial block loads memory contents from a text file (hex or other radix) at configuration time, controlled by an init_file parameter that defaults to null.
• Read-only memory: removing the write enable, write address, and write data logic from the same design turns it into ROM, useful for things like fixed instruction memory for a processor.

Walkthrough

Block RAM basics (0:32)

The lecture explains why flip-flops don't scale for storage, introduces embedded block RAM as a separate FPGA resource with configurable width and depth, and notes that the iCE40HX1K on the iCEstick has 16 blocks totaling 64 kilobits.

Designing the memory module (5:52)

A small 16-element, 8-bit-wide dual-port memory is defined with reg [7:0] mem [0:15]. A single always block, clocked on the positive edge, writes w_data to mem[w_addr] when w_en is high and copies mem[r_addr] to r_data when r_en is high, using one shared clock for both operations.

Checking device utilization (9:40)

Using a dummy .pcf file (so synthesis and place-and-route can run without uploading to hardware), apio build -v prints a device utilization chart showing logic cells, RAM blocks, I/O pins, and other resources used - confirming that even this small memory design consumes one full RAM block out of sixteen available.

Writing a test bench for the memory (12:07)

The test bench instantiates the memory module as the unit under test, generates a simulated ~12 MHz clock, and runs a sequence of reads and writes. A bug surfaces where an address of 4'h10 silently wraps to 0 because the address bus is only 4 bits wide - illustrating that Verilog truncates a constant to fit a signal's declared width.

Initializing memory from a file (19:29)

Rather than looping to set values in hardware, the lecture creates a plain text file of hex values and adds a synthesizable initial block using $readmemh, controlled by a parameter that defaults to null so initialization is opt-in. The test bench confirms every memory element loads the expected value at startup.

Read-only memory (24:27)

By removing the write enable, write address, and write data signals from the same module, the lecture turns it into read-only memory whose contents come entirely from the initialization file - framed as a way to store fixed instructions for a soft processor.

Before you watch

• Complete Part 7 ("Verilog Testbenches and Simulation"), since this lecture builds its memory test bench the same way.
• Having modules for a clock divider and button debouncer ready (from Parts 4-6) will help with this episode's LED-sequencer challenge.

Check your understanding

1. Why does declaring even a 16-element memory consume an entire 4Kb block RAM resource?
2. What causes the address bug the lecture finds in its own test bench, and how is it fixed?
3. What is the difference between how this design's memory behaves versus true read-only memory?
4. Why is $readmemh placed inside an initial block that is still considered synthesizable in this case?
5. What does the device utilization chart from apio build -v tell you about a design?