Lecture 6: Timing & Verification II

What this lecture covers

This lecture answers a practical question left open after the first timing lecture: once you know a circuit is logically correct, how do you know it is fast enough and correctly built? It continues the Digital Design & Computer Architecture course's timing unit, closing out the digital-design half before the course moves to Von Neumann architecture and instruction sets the following week.

You'll come away able to compute a circuit's contamination and propagation delay, explain why glitches occur and when to ignore them, derive the setup-time and hold-time constraints between two flip-flops (and fix a hold-time violation), account for clock skew, and describe how testbenches and golden models are used to verify a design's functionality and timing before it goes to hardware.

Key ideas

• Propagation delay: the time until a gate's output finishes changing after an input changes; used to compute the longest (critical) path through a circuit.
• Contamination delay: the time until a gate's output starts changing; used to compute the shortest path, and always calculated conservatively (best-case, fastest assumptions).
• Glitch: a single input transition that causes multiple output transitions because signals reach a gate through paths of different speed; usually safe to ignore if only the final steady-state value matters.
• Setup time and hold time: the windows before and after a clock edge during which a flip-flop's data input must stay stable, or the flip-flop can enter metastability.
• Sequencing overhead: the clock-to-Q propagation delay plus setup time that every cycle "wastes" on flip-flop timing rather than useful combinational work.
• Clock skew: the difference in arrival time of the clock edge at different flip-flops, which tightens both the effective setup and hold time requirements.
• Golden model: a trusted, high-level reference implementation used to automatically check a design under test's outputs during verification.
• Sequencing overhead vs. timing violations: a setup-time violation can be fixed by lowering the clock frequency; a hold-time violation cannot, and instead requires changing the circuit (for example adding buffers).

Walkthrough

Combinational circuit delay (6:09)

The lecture reintroduces why real gates aren't instantaneous: transistor switching, RC delay from parasitic capacitance and resistance, and even the finite speed of light all contribute to delay. It shows that rising and falling transitions can have different delays (illustrated with the CMOS NAND gate's series pull-down vs. parallel pull-up networks), and that temperature, supply voltage, and circuit aging all shift latency, so a designer deals with a range of possible delays rather than one fixed number.

Contamination delay and propagation delay (11:17)

Using a small multi-gate circuit, the lecture defines contamination delay (shortest-path, best-case) and propagation delay (longest-path, worst-case) precisely, then works through a numeric example where an input transition ripples through several gates to show how delay accumulates along the critical path. It also notes that real designs rarely have an obviously "longest" and "shortest" path — different input vectors, wire lengths, and manufacturing variation can all change which path is critical, which is why timing analysis is normally automated with CAD tools rather than done by hand.

Glitches (23:28)

A worked circuit shows an output flipping from one to zero and briefly back to one before settling, because a fast path and a slow path to the same gate disagree temporarily. The lecture explains that fixing glitches costs extra area, power, and design effort, and is usually unnecessary if only the long-term output matters — though glitches do waste dynamic power, which is one reason Moore machines are often preferred over Mealy machines in sequential design.

Setup time, hold time and metastability (29:34)

The lecture returns to the D flip-flop and defines setup time (data must be stable before the clock edge) and hold time (data must stay stable after it), together called the aperture time. Violating either can push the flip-flop into metastability, an unstable state between logic 0 and 1 that eventually resolves non-deterministically. It then defines the flip-flop's own contamination delay (clock-to-Q) and propagation delay (clock-to-Q) analogous to combinational gates.

Meeting setup and hold time constraints (40:42)

With two flip-flops connected by combinational logic, the lecture derives the minimum clock period from the setup-time constraint: clock period must exceed clock-to-Q propagation delay plus the combinational logic's propagation delay plus setup time. It separately derives the hold-time constraint using contamination delays, and shows — importantly — that this constraint doesn't involve clock period at all, so a hold-time violation can't be fixed by slowing the clock. A numeric example (four flip-flops, a three-gate combinational block) walks through computing the maximum frequency from the setup constraint and then finds and fixes a hold-time violation by inserting buffer gates to add contamination delay.

Clock skew (1:05:04)

Because clock signals travel different physical distances to different flip-flops, they arrive at slightly different times — clock skew, illustrated with a real skew map from an Alpha processor. The lecture shows how skew tightens the effective setup time (if the downstream register's clock arrives early) and effective hold time (if the upstream register's clock arrives early), adding to sequencing overhead. It briefly notes why clock networks are deliberately kept simple (undivided, uncomputed) to avoid worsening skew, unlike the earlier example of dividing a clock by three with an FSM.

Functional and timing verification (1:11:05)

The lecture shifts to verification: is a design functionally correct, and does it meet timing? It contrasts fast, high-level HDL/C simulation (used for functional checking) with slow, low-level circuit or SPICE simulation (used for timing and power), noting industry reports that verification can consume around 70% of design time. It walks through Verilog testbench styles of increasing sophistication — manual checking, self-checking assertions, file-based test vectors, and fully automatic testbenches that compare a device under test against a golden model — and closes with why exhaustive testing (for example of a 32-bit adder) is computationally infeasible, and how synthesis/place-and-route tools report timing failures that guide manual fixes such as splitting long combinational paths, balancing delays across pipeline stages, and optimizing for the common case.

Before you watch

• Be comfortable with basic combinational logic (AND/OR/NAND gates, Boolean circuits) and D flip-flop behavior from earlier lectures in this course.
• Review CMOS NAND gate structure (pull-up and pull-down networks), since it's used to explain asymmetric rising/falling delays.
• Recall Mealy and Moore machine differences, referenced when discussing glitches and combinational path length.

Check your understanding

1. Why is contamination delay always calculated using best-case (fastest) assumptions, while propagation delay uses worst-case assumptions?
2. A circuit has a hold-time violation between two flip-flops. Why can't you fix this by increasing the clock period, and what change could fix it instead?
3. How does clock skew affect the effective setup time differently depending on whether the downstream or upstream flip-flop's clock arrives earlier?
4. What is the difference between a self-checking testbench and a fully automatic testbench that uses a golden model?
5. Why is exhaustive (brute-force) testing infeasible for something as simple as a 32-bit adder, and what approaches does the lecture suggest instead?