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Digital Design & Computer Architecture · Lecture 8 of 37 · 1:49:42

Lecture 6: Timing & Verification II

Study guide

What this lecture covers

This lecture answers a practical question left open after the first timing lecture: once you know a circuit is logically correct, how do you know it is fast enough and correctly built? It continues the Digital Design & Computer Architecture course's timing unit, closing out the digital-design half before the course moves to Von Neumann architecture and instruction sets the following week.

You'll come away able to compute a circuit's contamination and propagation delay, explain why glitches occur and when to ignore them, derive the setup-time and hold-time constraints between two flip-flops (and fix a hold-time violation), account for clock skew, and describe how testbenches and golden models are used to verify a design's functionality and timing before it goes to hardware.

Key ideas

Propagation delay: the time until a gate's output finishes changing after an input changes; used to compute the longest (critical) path through a circuit.
Contamination delay: the time until a gate's output starts changing; used to compute the shortest path, and always calculated conservatively (best-case, fastest assumptions).
Glitch: a single input transition that causes multiple output transitions because signals reach a gate through paths of different speed; usually safe to ignore if only the final steady-state value matters.
Setup time and hold time: the windows before and after a clock edge during which a flip-flop's data input must stay stable, or the flip-flop can enter metastability.
Sequencing overhead: the clock-to-Q propagation delay plus setup time that every cycle "wastes" on flip-flop timing rather than useful combinational work.
Clock skew: the difference in arrival time of the clock edge at different flip-flops, which tightens both the effective setup and hold time requirements.
Golden model: a trusted, high-level reference implementation used to automatically check a design under test's outputs during verification.
Sequencing overhead vs. timing violations: a setup-time violation can be fixed by lowering the clock frequency; a hold-time violation cannot, and instead requires changing the circuit (for example adding buffers).

Walkthrough

Combinational circuit delay (6:09)

The lecture reintroduces why real gates aren't instantaneous: transistor switching, RC delay from parasitic capacitance and resistance, and even the finite speed of light all contribute to delay. It shows that rising and falling transitions can have different delays (illustrated with the CMOS NAND gate's series pull-down vs. parallel pull-up networks), and that temperature, supply voltage, and circuit aging all shift latency, so a designer deals with a range of possible delays rather than one fixed number.

Contamination delay and propagation delay (11:17)

Using a small multi-gate circuit, the lecture defines contamination delay (shortest-path, best-case) and propagation delay (longest-path, worst-case) precisely, then works through a numeric example where an input transition ripples through several gates to show how delay accumulates along the critical path. It also notes that real designs rarely have an obviously "longest" and "shortest" path — different input vectors, wire lengths, and manufacturing variation can all change which path is critical, which is why timing analysis is normally automated with CAD tools rather than done by hand.

Glitches (23:28)

A worked circuit shows an output flipping from one to zero and briefly back to one before settling, because a fast path and a slow path to the same gate disagree temporarily. The lecture explains that fixing glitches costs extra area, power, and design effort, and is usually unnecessary if only the long-term output matters — though glitches do waste dynamic power, which is one reason Moore machines are often preferred over Mealy machines in sequential design.

Setup time, hold time and metastability (29:34)

The lecture returns to the D flip-flop and defines setup time (data must be stable before the clock edge) and hold time (data must stay stable after it), together called the aperture time. Violating either can push the flip-flop into metastability, an unstable state between logic 0 and 1 that eventually resolves non-deterministically. It then defines the flip-flop's own contamination delay (clock-to-Q) and propagation delay (clock-to-Q) analogous to combinational gates.

Meeting setup and hold time constraints (40:42)

With two flip-flops connected by combinational logic, the lecture derives the minimum clock period from the setup-time constraint: clock period must exceed clock-to-Q propagation delay plus the combinational logic's propagation delay plus setup time. It separately derives the hold-time constraint using contamination delays, and shows — importantly — that this constraint doesn't involve clock period at all, so a hold-time violation can't be fixed by slowing the clock. A numeric example (four flip-flops, a three-gate combinational block) walks through computing the maximum frequency from the setup constraint and then finds and fixes a hold-time violation by inserting buffer gates to add contamination delay.

Clock skew (1:05:04)

Because clock signals travel different physical distances to different flip-flops, they arrive at slightly different times — clock skew, illustrated with a real skew map from an Alpha processor. The lecture shows how skew tightens the effective setup time (if the downstream register's clock arrives early) and effective hold time (if the upstream register's clock arrives early), adding to sequencing overhead. It briefly notes why clock networks are deliberately kept simple (undivided, uncomputed) to avoid worsening skew, unlike the earlier example of dividing a clock by three with an FSM.

Functional and timing verification (1:11:05)

The lecture shifts to verification: is a design functionally correct, and does it meet timing? It contrasts fast, high-level HDL/C simulation (used for functional checking) with slow, low-level circuit or SPICE simulation (used for timing and power), noting industry reports that verification can consume around 70% of design time. It walks through Verilog testbench styles of increasing sophistication — manual checking, self-checking assertions, file-based test vectors, and fully automatic testbenches that compare a device under test against a golden model — and closes with why exhaustive testing (for example of a 32-bit adder) is computationally infeasible, and how synthesis/place-and-route tools report timing failures that guide manual fixes such as splitting long combinational paths, balancing delays across pipeline stages, and optimizing for the common case.

Before you watch

Be comfortable with basic combinational logic (AND/OR/NAND gates, Boolean circuits) and D flip-flop behavior from earlier lectures in this course.
Review CMOS NAND gate structure (pull-up and pull-down networks), since it's used to explain asymmetric rising/falling delays.
Recall Mealy and Moore machine differences, referenced when discussing glitches and combinational path length.

Check your understanding

Why is contamination delay always calculated using best-case (fastest) assumptions, while propagation delay uses worst-case assumptions?
A circuit has a hold-time violation between two flip-flops. Why can't you fix this by increasing the clock period, and what change could fix it instead?
How does clock skew affect the effective setup time differently depending on whether the downstream or upstream flip-flop's clock arrives earlier?
What is the difference between a self-checking testbench and a fully automatic testbench that uses a golden model?
Why is exhaustive (brute-force) testing infeasible for something as simple as a 32-bit adder, and what approaches does the lecture suggest instead?

Vocabulary

contamination delay (noun): The shortest time before a gate's output starts to change after an input changes.
Contamination delay is always calculated using best-case assumptions.
propagation delay (noun): The longest time until a gate's output finishes changing after an input changes.
The critical path's total propagation delay limits how fast the circuit can run.
critical path (noun): The slowest route through a circuit, whose delay decides the circuit's maximum speed.
We compute the circuit's timing along the critical path.
RC delay (noun): Delay caused by resistance and capacitance slowing down how fast a signal can change.
Parasitic capacitance causes RC delay in real transistors.
parasitic capacitance (noun): Unwanted capacitance that naturally exists in wires and transistors and slows signals.
Parasitic capacitance adds delay that ideal circuit diagrams ignore.
CMOS (noun): A common technology for building logic gates using paired transistor types.
The CMOS NAND gate has a pull-down and a pull-up network.
pull-down network (noun): The part of a CMOS gate that connects the output to ground (logic 0).
The NAND gate's series pull-down network is slower than its parallel pull-up.
pull-up network (noun): The part of a CMOS gate that connects the output to the supply voltage (logic 1).
The pull-up network determines the rising-edge delay.
manufacturing variation (noun): Small random differences between chips caused by imperfections in the manufacturing process.
Manufacturing variation means delay is a range, not one fixed number.
glitch (noun): An extra, unwanted output change caused by signals arriving through paths of different speed.
A glitch briefly flips the output before it settles at the correct value.
dynamic power (noun): Power used by a circuit each time a signal switches between 0 and 1.
Glitches waste dynamic power even though the final output is correct.
setup time (noun): The minimum time data must stay stable before a clock edge for a flip-flop to capture it correctly.
Violating setup time can cause the flip-flop to capture the wrong value.
hold time (noun): The minimum time data must stay stable after a clock edge for a flip-flop to capture it correctly.
A hold-time violation cannot be fixed by slowing down the clock.
aperture time (noun): The full window around a clock edge, combining setup time and hold time, during which data must be stable.
Together, setup and hold time make up the flip-flop's aperture time.
metastability (noun): An unstable state where a flip-flop's output sits between 0 and 1 and settles unpredictably.
Violating setup or hold time can push a flip-flop into metastability.
clock-to-Q delay (noun): The time between a clock edge and when a flip-flop's output actually changes.
Clock-to-Q propagation delay adds to the circuit's sequencing overhead.
sequencing overhead (noun): The time each clock cycle loses to flip-flop timing rather than to useful logic work.
Clock-to-Q delay plus setup time make up the sequencing overhead.
clock skew (noun): The difference in arrival time of the clock signal at different flip-flops.
Clock skew tightens the effective setup and hold time margins.
buffer (noun): A simple gate added to a circuit mainly to add delay or restore signal strength, without changing logic.
Adding a buffer increases contamination delay to fix a hold-time violation.
golden model (noun): A trusted reference implementation used to automatically check whether a design's outputs are correct.
The automatic testbench compares the design against a golden model.
device under test (noun): The circuit or design currently being tested.
The testbench feeds inputs to the device under test and checks the results.
SPICE simulation (noun): A slow, very detailed circuit simulation used to check exact timing and power.
SPICE simulation is used for timing and power, not fast functional checks.
exhaustive testing (noun): Testing every single possible input combination of a design.
Exhaustive testing of a 32-bit adder is computationally infeasible.
infeasible (adjective): Not possible to do in practice, usually because it would take too much time or resources.
Checking every input of a wide adder is infeasible by hand.
pipeline stage (noun): One step of a multi-step process where a task is divided into sequential parts.
Balancing delays across pipeline stages improves overall speed.
place-and-route (noun): The step where a synthesized circuit's gates are positioned on a chip and connected with wires.
Place-and-route tools report which paths fail timing.

From the YouTube description

Digital Design and Computer Architecture, ETH Zürich, Spring 2025 (https://safari.ethz.ch/ddca/spring2025/)

Lecture 6: Timing & Verification II
Lecturer: Prof. Onur Mutlu
Date: 7 March 2025

Lecture 6 Slides (pptx): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture6-timing-and-verification-ii-afterlecture.pptx
Lecture 6 Slides (pdf): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture6-timing-and-verification-ii-afterlecture.pdf

Recommended Reading:
====================
Intelligent Architectures for Intelligent Computing Systems
https://people.inf.ethz.ch/omutlu/pub/intelligent-architectures-for-intelligent-computingsystems-invited_paper_DATE21.pdf

A Modern Primer on Processing in Memory
https://people.inf.ethz.ch/omutlu/pub/ModernPrimerOnPIM_springer-emerging-computing-bookchapter21.pdf

RowHammer: A Retrospective
https://people.inf.ethz.ch/omutlu/pub/RowHammer-Retrospective_ieee_tcad19.pdf

RECOMMENDED LECTURE VIDEOS & PLAYLISTS:
========================================
Computer Architecture Fall 2021 Lectures Playlist:
https://www.youtube.com/watch?v=4yfkM_5EFgo&list=PL5Q2soXY2Zi-Mnk1PxjEIG32HAGILkTOF

Computer Architecture Fall 2022 Lectures Playlist:
https://www.youtube.com/watch?v=BIpPTqHK-Lc&list=PL5Q2soXY2Zi-cAls3cyauNzM7-74Eq31O

Digital Design and Computer Architecture Spring 2022 Livestream Lectures Playlist:
https://www.youtube.com/watch?v=cpXdE3HwvK0&list=PL5Q2soXY2Zi97Ya5DEUpMpO2bbAoaG7c6

Digital Design and Computer Architecture Spring 2021 Livestream Lectures Playlist:
https://www.youtube.com/watch?v=LbC0EZY8yw4&list=PL5Q2soXY2Zi_uej3aY39YB5pfW4SJ7LlN

Featured Lectures:
https://www.youtube.com/watch?v=jVYCchBGNVc&list=PL5Q2soXY2Zi8VrmOTz44l2WupethSdh-M&index=1

Interview with Professor Onur Mutlu:
https://www.youtube.com/watch?v=8ffSEKZhmvo&list=PL5Q2soXY2Zi8VrmOTz44l2WupethSdh-M&index=9

The Story of RowHammer Lecture:
https://www.youtube.com/watch?v=sgd7PHQQ1AI&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=39

Accelerating Genome Analysis Lecture:
https://www.youtube.com/watch?v=r7sn41lH-4A&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=41

Memory-Centric Computing Systems Tutorial at IEDM 2021:
https://www.youtube.com/watch?v=H3sEaINPBOE&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=35

Intelligent Architectures for Intelligent Machines Lecture:
https://www.youtube.com/watch?v=GTieZPY4Wmc&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=38

Computer Architecture Fall 2020 Lectures Playlist:
https://www.youtube.com/watch?v=c3mPdZA-Fmc&list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN

Digital Design and Computer Architecture Spring 2020 Lectures Playlist:
https://www.youtube.com/watch?v=AJBmIaUneB0&list=PL5Q2soXY2Zi_FRrloMa2fUYWPGiZUBQo2

Public Lectures by Onur Mutlu, Playlist:
https://www.youtube.com/watch?v=kgiZlSOcGFM&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl

Computer Architecture at Carnegie Mellon Spring 2015 Lectures Playlist:
https://www.youtube.com/watch?v=zLP_X4wyHbY&list=PL5PHm2jkkXmi5CxxI7b3JCL1TWybTDtKq

Rethinking Memory System Design Lecture @stanfordonline :
https://www.youtube.com/watch?v=F7xZLNMIY1E&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=4

← Lecture 5: HDL, Verilog II, Timing and Verification · Lecture 7: Von Neumann Model & Instruction Set Architectures →