Lecture 5: HDL, Verilog II, Timing and Verification

What this lecture covers

This lecture answers a practical question: how do you actually write Verilog code that describes real digital hardware, including sequential circuits, rather than code that merely looks correct but does not map to real gates? It continues directly from the previous lecture's introduction to Verilog modules, covering bit manipulation syntax, the difference between structural and behavioral modeling, number and tri-state notation, and the crucial gap between simulating and synthesizing HDL code. The second half shows how to describe sequential logic and finite state machines (FSMs) in Verilog using always blocks, blocking and non-blocking assignments, before a short preview of the next lecture's timing and verification topic.

This is the course's second Verilog lecture, building directly on module definitions and port declarations from the prior session, and on the FSM design concepts (Moore vs. Mealy, state registers) covered earlier in the course. After watching, you should be able to write both structural and behavioral Verilog for combinational logic, correctly use always blocks to describe flip-flops, latches, and combinational logic, and implement a simple FSM in Verilog.

Key ideas

• Structural (gate-level) modeling: describing a circuit as instantiated gates or submodules and their interconnections.
• Behavioral modeling: describing circuit functionality with equations, conditional expressions, and operators, at a higher level of abstraction than gates.
• Synthesizable vs. simulation-only code: constructs like explicit gate delays model timing for simulation but cannot be turned into real hardware by a synthesis tool.
• always block: the Verilog construct for sequential and combinational logic outside plain assign statements, triggered by a sensitivity list.
• Blocking vs. non-blocking assignment: non-blocking assignments (<=) evaluate all right-hand sides using old values and update in parallel at the end of the block, which is why they are preferred for sequential logic; blocking assignments (=) execute strictly in order.
• Unintended latches: an always block only describes combinational logic if every output is assigned in every possible branch; missing cases synthesize as memory (a latch) even when that was not intended.
• Parameters: named constants (#parameter) that let a module's bit widths be reused for different sizes without rewriting the code.

Walkthrough

Verilog syntax essentials: bit slicing, concatenation, and comments (9:42)

After a quick recap of module definitions and port declarations from the prior lecture, the lecture introduces core Verilog syntax for manipulating bits: slicing a range out of a wider bus (for example, assigning bits 12 down to 5 of a 16-bit bus to an 8-bit bus), concatenating multiple signals into a wider vector, and using a duplication shorthand to repeat a signal several times. It also notes that Verilog is case-sensitive, identifiers cannot start with a digit, whitespace is ignored, and comments use // for single lines and /* */ for multiple lines.

Structural vs. behavioral modeling and module instantiation (12:46)

The lecture distinguishes two main HDL styles: structural (gate-level) modeling, where a module's body instantiates gates or submodules and wires them together, and behavioral modeling, where the body describes functionality with logical and mathematical operators. Most practical designs mix both. A worked example shows a top module instantiating two copies of a smaller submodule, connecting ports by name (preferred, for readability and robustness) rather than by position, and using an internal wire to connect the two instances in sequence.

Predefined gate primitives and behavioral assign statements (21:54)

Verilog provides basic logic gates (and, or, not, and others) as predefined primitives that can be instantiated directly without defining a module, with the convention that the first signal listed is the output and the rest are inputs. A two-to-one multiplexer is built this way from not, and, and or primitives. The lecture then contrasts this with behavioral modeling using the assign keyword and Boolean equations, bitwise and reduction operators (such as reducing a whole bit vector with a single AND), and the ternary conditional operator, which is used to build multiplexers concisely, including a 4-to-1 multiplexer using nested conditionals.

Numbers, don't-cares, and tri-state signals in Verilog (32:07)

Verilog number literals follow a bits'base value format (for example, 4'b1001), where the base can be binary, hexadecimal, decimal, or octal, and values can include x for don't-care/invalid and z for a floating (high-impedance) signal. If the specified number of bits exceeds what is written, the value is zero-padded, and a number written without an explicit width defaults to 32 bits. The lecture connects this to tri-state buffers on a shared bus (for example, a CPU and memory both connecting to a shared memory bus) and shows the truth table for logic gates when inputs include z or x.

Synthesis vs. simulation, and writing HDL to describe hardware (37:08)

The lecture separates two uses of HDL code: synthesizing it into a real gate-level circuit (with optimization against constraints like target frequency or area, which synthesis tools cannot guarantee is optimal) and simulating it to verify functional and timing behavior before manufacturing anything. It stresses a central warning, echoed from the textbook: a beginner's most common mistake is treating HDL as a regular program rather than a shorthand for hardware structure, which can produce code that simulates correctly but either wastes hardware or cannot be implemented at all. A worked equality-checker example shows the same functionality written at several abstraction levels, from fully explicit gate instantiation down to a single ternary assign, illustrating the trade-off between low-level control and high-level readability.

Sequential logic in Verilog: always blocks, blocking vs. non-blocking assignment (1:09:07)

The lecture introduces the always block, Verilog's construct for describing logic that plain assign statements cannot express well, particularly memory elements. A D flip-flop is written with always @(posedge clock) and a non-blocking assignment; asynchronous and synchronous reset variants, and an enabled flip-flop, are shown as extensions. A key rule is emphasized: any signal assigned inside an always block must be declared as reg, and an always block only describes combinational logic (rather than an unintended latch) if every output is assigned in every possible branch of every if/case statement, which Vivado will typically warn about if violated. The lecture then contrasts blocking (=) and non-blocking (<=) assignment: non-blocking assignments all read old values and update concurrently at the end of the block, matching hardware's inherent concurrency, while blocking assignments execute strictly in sequence, which can require extra simulation iterations to converge to the same result and is generally reserved for simple combinational logic.

Implementing FSMs in Verilog with worked examples (1:35:31)

The lecture ties the sequential-logic constructs together to implement full FSMs in Verilog, using a clock-divide-by-three FSM and the course's recurring "smiling snail" pattern-detector FSM as examples. Each FSM is written as three parts: a state register (always @(posedge clock or posedge reset) with non-blocking assignment to the state), a combinational always block with a case statement for next-state logic (including a default case to avoid unreachable-state bugs from unused encodings), and an output assign statement. The lecture closes the Verilog topic and gives a short preview of the next lecture on timing and verification, previewing concepts like propagation delay, setup and hold time, and design trade-offs among area, speed, and power.

Before you watch

• Review the prior lecture's coverage of Verilog module syntax (ports, port lists, bit-range declarations), since this lecture builds directly on it without re-explaining the basics.
• Be comfortable with the Moore vs. Mealy FSM distinction and state-register concepts from the earlier sequential-logic lectures, since the FSM examples assume this background.

Check your understanding

1. Why does an always block sometimes synthesize into an unintended latch, and how does adding a default case help avoid this?
2. What is the practical difference between blocking and non-blocking assignment, and why is non-blocking assignment preferred for sequential logic?
3. Why can a signal delay specified in Verilog (such as a 5-nanosecond delay) be used in a testbench but not in code meant to be synthesized?
4. In the equality-checker example, what is the trade-off between writing fully explicit gate-level Verilog versus a single behavioral assign statement?
5. Why does the state register in an FSM need a default case in its next-state logic when the state is encoded with more bit patterns than there are states?