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Digital Design & Computer Architecture · Lecture 7 of 37 · 1:48:14

Lecture 5: HDL, Verilog II, Timing and Verification

Study guide

What this lecture covers

This lecture answers a practical question: how do you actually write Verilog code that describes real digital hardware, including sequential circuits, rather than code that merely looks correct but does not map to real gates? It continues directly from the previous lecture's introduction to Verilog modules, covering bit manipulation syntax, the difference between structural and behavioral modeling, number and tri-state notation, and the crucial gap between simulating and synthesizing HDL code. The second half shows how to describe sequential logic and finite state machines (FSMs) in Verilog using always blocks, blocking and non-blocking assignments, before a short preview of the next lecture's timing and verification topic.

This is the course's second Verilog lecture, building directly on module definitions and port declarations from the prior session, and on the FSM design concepts (Moore vs. Mealy, state registers) covered earlier in the course. After watching, you should be able to write both structural and behavioral Verilog for combinational logic, correctly use always blocks to describe flip-flops, latches, and combinational logic, and implement a simple FSM in Verilog.

Key ideas

Structural (gate-level) modeling: describing a circuit as instantiated gates or submodules and their interconnections.
Behavioral modeling: describing circuit functionality with equations, conditional expressions, and operators, at a higher level of abstraction than gates.
Synthesizable vs. simulation-only code: constructs like explicit gate delays model timing for simulation but cannot be turned into real hardware by a synthesis tool.
always block: the Verilog construct for sequential and combinational logic outside plain assign statements, triggered by a sensitivity list.
Blocking vs. non-blocking assignment: non-blocking assignments (<=) evaluate all right-hand sides using old values and update in parallel at the end of the block, which is why they are preferred for sequential logic; blocking assignments (=) execute strictly in order.
Unintended latches: an always block only describes combinational logic if every output is assigned in every possible branch; missing cases synthesize as memory (a latch) even when that was not intended.
Parameters: named constants (#parameter) that let a module's bit widths be reused for different sizes without rewriting the code.

Walkthrough

Verilog syntax essentials: bit slicing, concatenation, and comments (9:42)

After a quick recap of module definitions and port declarations from the prior lecture, the lecture introduces core Verilog syntax for manipulating bits: slicing a range out of a wider bus (for example, assigning bits 12 down to 5 of a 16-bit bus to an 8-bit bus), concatenating multiple signals into a wider vector, and using a duplication shorthand to repeat a signal several times. It also notes that Verilog is case-sensitive, identifiers cannot start with a digit, whitespace is ignored, and comments use // for single lines and /* */ for multiple lines.

Structural vs. behavioral modeling and module instantiation (12:46)

The lecture distinguishes two main HDL styles: structural (gate-level) modeling, where a module's body instantiates gates or submodules and wires them together, and behavioral modeling, where the body describes functionality with logical and mathematical operators. Most practical designs mix both. A worked example shows a top module instantiating two copies of a smaller submodule, connecting ports by name (preferred, for readability and robustness) rather than by position, and using an internal wire to connect the two instances in sequence.

Predefined gate primitives and behavioral assign statements (21:54)

Verilog provides basic logic gates (and, or, not, and others) as predefined primitives that can be instantiated directly without defining a module, with the convention that the first signal listed is the output and the rest are inputs. A two-to-one multiplexer is built this way from not, and, and or primitives. The lecture then contrasts this with behavioral modeling using the assign keyword and Boolean equations, bitwise and reduction operators (such as reducing a whole bit vector with a single AND), and the ternary conditional operator, which is used to build multiplexers concisely, including a 4-to-1 multiplexer using nested conditionals.

Numbers, don't-cares, and tri-state signals in Verilog (32:07)

Verilog number literals follow a bits'base value format (for example, 4'b1001), where the base can be binary, hexadecimal, decimal, or octal, and values can include x for don't-care/invalid and z for a floating (high-impedance) signal. If the specified number of bits exceeds what is written, the value is zero-padded, and a number written without an explicit width defaults to 32 bits. The lecture connects this to tri-state buffers on a shared bus (for example, a CPU and memory both connecting to a shared memory bus) and shows the truth table for logic gates when inputs include z or x.

Synthesis vs. simulation, and writing HDL to describe hardware (37:08)

The lecture separates two uses of HDL code: synthesizing it into a real gate-level circuit (with optimization against constraints like target frequency or area, which synthesis tools cannot guarantee is optimal) and simulating it to verify functional and timing behavior before manufacturing anything. It stresses a central warning, echoed from the textbook: a beginner's most common mistake is treating HDL as a regular program rather than a shorthand for hardware structure, which can produce code that simulates correctly but either wastes hardware or cannot be implemented at all. A worked equality-checker example shows the same functionality written at several abstraction levels, from fully explicit gate instantiation down to a single ternary assign, illustrating the trade-off between low-level control and high-level readability.

Sequential logic in Verilog: always blocks, blocking vs. non-blocking assignment (1:09:07)

The lecture introduces the always block, Verilog's construct for describing logic that plain assign statements cannot express well, particularly memory elements. A D flip-flop is written with always @(posedge clock) and a non-blocking assignment; asynchronous and synchronous reset variants, and an enabled flip-flop, are shown as extensions. A key rule is emphasized: any signal assigned inside an always block must be declared as reg, and an always block only describes combinational logic (rather than an unintended latch) if every output is assigned in every possible branch of every if/case statement, which Vivado will typically warn about if violated. The lecture then contrasts blocking (=) and non-blocking (<=) assignment: non-blocking assignments all read old values and update concurrently at the end of the block, matching hardware's inherent concurrency, while blocking assignments execute strictly in sequence, which can require extra simulation iterations to converge to the same result and is generally reserved for simple combinational logic.

Implementing FSMs in Verilog with worked examples (1:35:31)

The lecture ties the sequential-logic constructs together to implement full FSMs in Verilog, using a clock-divide-by-three FSM and the course's recurring "smiling snail" pattern-detector FSM as examples. Each FSM is written as three parts: a state register (always @(posedge clock or posedge reset) with non-blocking assignment to the state), a combinational always block with a case statement for next-state logic (including a default case to avoid unreachable-state bugs from unused encodings), and an output assign statement. The lecture closes the Verilog topic and gives a short preview of the next lecture on timing and verification, previewing concepts like propagation delay, setup and hold time, and design trade-offs among area, speed, and power.

Before you watch

Review the prior lecture's coverage of Verilog module syntax (ports, port lists, bit-range declarations), since this lecture builds directly on it without re-explaining the basics.
Be comfortable with the Moore vs. Mealy FSM distinction and state-register concepts from the earlier sequential-logic lectures, since the FSM examples assume this background.

Check your understanding

Why does an always block sometimes synthesize into an unintended latch, and how does adding a default case help avoid this?
What is the practical difference between blocking and non-blocking assignment, and why is non-blocking assignment preferred for sequential logic?
Why can a signal delay specified in Verilog (such as a 5-nanosecond delay) be used in a testbench but not in code meant to be synthesized?
In the equality-checker example, what is the trade-off between writing fully explicit gate-level Verilog versus a single behavioral assign statement?
Why does the state register in an FSM need a default case in its next-state logic when the state is encoded with more bit patterns than there are states?

Vocabulary

structural modeling (noun): Describing a circuit by naming and connecting gates or smaller modules together.
Structural modeling instantiates gates and wires them by hand.
behavioral modeling (noun): Describing what a circuit does using equations and logic operators, without listing individual gates.
Behavioral modeling uses assign statements instead of gate names.
instantiate (verb): To create one specific copy of a module or gate inside a design.
The top module instantiates two copies of the smaller submodule.
synthesizable (adjective): Able to be turned into a real hardware circuit by a synthesis tool.
Explicit delay statements are not synthesizable.
simulation (noun): Running a design description on a computer to check its behavior before building real hardware.
Delay values are useful in simulation but not in real hardware.
always block (noun): A Verilog code block that runs whenever the signals in its trigger list change.
Sequential logic in Verilog is written inside an always block.
sensitivity list (noun): The list of signals that, when they change, cause an always block to run again.
The always block's sensitivity list includes the clock edge.
blocking assignment (noun): A Verilog assignment (=) that happens immediately, in the exact order written.
Blocking assignment executes each line before moving to the next.
non-blocking assignment (noun): A Verilog assignment (<=) where all right sides use old values and every update happens together at the end.
Non-blocking assignment is used to model flip-flops correctly.
unintended latch (noun): A memory element created by mistake because a Verilog block does not assign a value in every possible case.
A missing else branch can create an unintended latch.
parameter (noun): A named constant in Verilog that can be reused to change a module's size without rewriting it.
A parameter lets the same adder module work for different bit widths.
bit slicing (noun): Selecting a smaller range of bits out of a wider signal.
Bit slicing takes bits 12 down to 5 from a 16-bit bus.
concatenation (noun): Joining several signals together end to end to form one wider signal.
Concatenation combines two 8-bit signals into one 16-bit signal.
case-sensitive (adjective): Treating uppercase and lowercase letters as different characters.
Verilog is case-sensitive, so Clock and clock are different signals.
wire (noun): A Verilog data type used to connect signals between gates or modules.
An internal wire connects the output of one instance to the input of the next.
reg (noun): A Verilog data type used for a signal that is assigned a value inside an always block.
Any signal assigned inside an always block must be declared as reg.
primitive (noun): A basic, ready-made logic gate built into the Verilog language.
The and, or, and not primitives can be used without defining a module.
multiplexer (noun): A circuit that selects one of several input signals to pass through to its output.
A two-to-one multiplexer is built from not, and, and or gates.
ternary conditional operator (noun): An operator that picks between two values based on a condition, written as condition ? a : b.
The ternary conditional operator builds a compact multiplexer.
reduction operator (noun): An operator that combines all bits of one signal into a single output bit.
A reduction AND checks whether every bit of the vector is 1.
don't-care value (noun): A value written as x in Verilog meaning the exact bit does not matter or is unknown.
An x in a Verilog literal marks a don't-care value.
high-impedance (adjective): Describes a signal disconnected from driving the wire, so it floats instead of being 0 or 1.
The z value represents a high-impedance, floating signal.
tri-state buffer (noun): A gate that can pass a signal through or disconnect it entirely, useful for a shared bus.
A tri-state buffer lets the CPU and memory share the same bus.
zero-padded (adjective): Filled with extra zero bits at the front to reach a required width.
A short binary literal is zero-padded to fill the declared width.
testbench (noun): A piece of code written to test another circuit design by feeding it inputs and checking outputs.
The testbench applies inputs and checks the equality checker's output.
abstraction level (noun): How much low-level detail a description shows versus hides.
The equality checker is shown at several abstraction levels.
posedge (noun): The moment a clock signal rises from 0 to 1.
The flip-flop is written with always @(posedge clock).
asynchronous reset (noun): A reset signal that takes effect immediately, regardless of the clock.
An asynchronous reset clears the flip-flop as soon as it activates.
synchronous reset (noun): A reset signal that only takes effect at the next clock edge.
A synchronous reset variant waits for the clock edge to clear the state.
default case (noun): A fallback branch in a case statement that covers any input not explicitly listed.
A default case avoids bugs from unused state encodings.
converge (verb): To settle to a final, stable value after some steps.
Blocking assignments can need extra iterations to converge.
clock divide (noun): A circuit that produces a slower clock signal from a faster one.
The clock-divide-by-three FSM outputs a signal three times slower than the input clock.
state machine (noun): See finite state machine: a circuit that moves through a fixed set of states.
The pattern-detector state machine watches for a specific bit sequence.

From the YouTube description

Digital Design and Computer Architecture, ETH Zürich, Spring 2025 (https://safari.ethz.ch/ddca/spring2025/)

Lecture 5a: Hardware Description Languages and Verilog II
Lecture 5b: Timing and Verification
Lecturer: Prof. Onur Mutlu
Date: 6 March 2025

Lecture 5a Slides (pptx): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture5a-hdl-verilog-ii-afterlecture.pptx
Lecture 5a Slides (pdf): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture5a-hdl-verilog-ii-afterlecture.pdf

Lecture 5b Slides (pptx): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture5b-timing-and-verification-afterlecture.pptx
Lecture 5b Slides (pdf): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture5b-timing-and-verification-afterlecture.pdf

Recommended Reading:
====================
Intelligent Architectures for Intelligent Computing Systems
https://people.inf.ethz.ch/omutlu/pub/intelligent-architectures-for-intelligent-computingsystems-invited_paper_DATE21.pdf

A Modern Primer on Processing in Memory
https://people.inf.ethz.ch/omutlu/pub/ModernPrimerOnPIM_springer-emerging-computing-bookchapter21.pdf

RowHammer: A Retrospective
https://people.inf.ethz.ch/omutlu/pub/RowHammer-Retrospective_ieee_tcad19.pdf

RECOMMENDED LECTURE VIDEOS & PLAYLISTS:
========================================
Computer Architecture Fall 2021 Lectures Playlist:
https://www.youtube.com/watch?v=4yfkM_5EFgo&list=PL5Q2soXY2Zi-Mnk1PxjEIG32HAGILkTOF

Computer Architecture Fall 2022 Lectures Playlist:
https://www.youtube.com/watch?v=BIpPTqHK-Lc&list=PL5Q2soXY2Zi-cAls3cyauNzM7-74Eq31O

Digital Design and Computer Architecture Spring 2022 Livestream Lectures Playlist:
https://www.youtube.com/watch?v=cpXdE3HwvK0&list=PL5Q2soXY2Zi97Ya5DEUpMpO2bbAoaG7c6

Digital Design and Computer Architecture Spring 2021 Livestream Lectures Playlist:
https://www.youtube.com/watch?v=LbC0EZY8yw4&list=PL5Q2soXY2Zi_uej3aY39YB5pfW4SJ7LlN

Featured Lectures:
https://www.youtube.com/watch?v=jVYCchBGNVc&list=PL5Q2soXY2Zi8VrmOTz44l2WupethSdh-M&index=1

Interview with Professor Onur Mutlu:
https://www.youtube.com/watch?v=8ffSEKZhmvo&list=PL5Q2soXY2Zi8VrmOTz44l2WupethSdh-M&index=9

The Story of RowHammer Lecture:
https://www.youtube.com/watch?v=sgd7PHQQ1AI&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=39

Accelerating Genome Analysis Lecture:
https://www.youtube.com/watch?v=r7sn41lH-4A&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=41

Memory-Centric Computing Systems Tutorial at IEDM 2021:
https://www.youtube.com/watch?v=H3sEaINPBOE&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=35

Intelligent Architectures for Intelligent Machines Lecture:
https://www.youtube.com/watch?v=GTieZPY4Wmc&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=38

Computer Architecture Fall 2020 Lectures Playlist:
https://www.youtube.com/watch?v=c3mPdZA-Fmc&list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN

Digital Design and Computer Architecture Spring 2020 Lectures Playlist:
https://www.youtube.com/watch?v=AJBmIaUneB0&list=PL5Q2soXY2Zi_FRrloMa2fUYWPGiZUBQo2

Public Lectures by Onur Mutlu, Playlist:
https://www.youtube.com/watch?v=kgiZlSOcGFM&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl

Computer Architecture at Carnegie Mellon Spring 2015 Lectures Playlist:
https://www.youtube.com/watch?v=zLP_X4wyHbY&list=PL5PHm2jkkXmi5CxxI7b3JCL1TWybTDtKq

Rethinking Memory System Design Lecture @stanfordonline :
https://www.youtube.com/watch?v=F7xZLNMIY1E&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=4

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