Lecture 7: Von Neumann Model & Instruction Set Architectures

What this lecture covers

This lecture opens the computer-architecture portion of the course after three weeks of digital design. It asks how a computer actually executes a program: what components does it need, how does it represent instructions as bits, and how does it step through them one at a time? The lecture builds from Von Neumann's 1946 model up to concrete instruction encodings in two example instruction set architectures (ISAs), LC-3 and MIPS, and ends by walking through how a single instruction moves through fetch, decode, and execute stages in hardware.

By the end, you can describe the five components of the Von Neumann model, explain memory addressing concepts (address space, addressability, byte vs. word addressing, endianness), read and hand-encode simple LC-3 and MIPS instructions, and trace how the LC-3 microarchitecture executes an ADD or LDR instruction using registers, an ALU, and a finite state machine controller.

Key ideas

• Von Neumann model: a computing model with five components — memory, a processing unit, input, output, and a control unit — where memory holds both instructions and data with no inherent distinction between them.
• Stored-program and sequential execution: the two defining properties of Von Neumann machines — instructions live in memory as data, and the program counter normally advances sequentially except for control-flow instructions.
• Address space and addressability: address space is the number of uniquely addressable locations; addressability is how many bits each address refers to (for example LC-3 is word-addressable with 16-bit words, MIPS is byte-addressable).
• Registers as fast temporary storage: a small register file sits next to the ALU so intermediate results don't need slow round-trips to main memory.
• Opcode and operand: every instruction encodes what to do (opcode) and what to do it to (operand), with the exact bit layout defined by the ISA specification.
• Endianness: big-endian stores the most significant byte at the lowest address, little-endian stores the least significant byte there; it only matters when systems using different conventions communicate.
• Instruction processing cycle: fetch, decode, evaluate address, fetch operand, execute, store result — not every instruction uses every phase (for example ADD skips address evaluation).
• Control-flow instructions: instructions like jump can load a new value directly into the program counter, letting execution deviate from strict sequential order.

Walkthrough

From digital design to computer architecture (4:50)

The lecture marks the transition from digital design (transistors, gates, sequential circuits, timing) to computer architecture, and introduces the plan: the Von Neumann model today, instruction set architectures using LC-3 and MIPS as running examples, and assembly programming starting the next lecture, before microarchitecture begins the following week.

The Von Neumann model (9:56)

John Von Neumann's 1946 model is introduced as the dominant (though not only) model for general-purpose computing: memory, a processing unit, input, output, and a control unit. Memory stores programs and data indistinguishably as bits; the control unit is what decides, based on context, whether a given memory location is being treated as an instruction or as data.

Memory: addressing and endianness (15:03)

The lecture defines address space (LC-3: 2^16, MIPS: 2^32) and addressability (bit-, byte-, or word-addressable), and works through examples of word-addressable versus byte-addressable memory layouts. It also covers big-endian versus little-endian byte ordering — using Gulliver's Travels' "Big-Endian"/"Little-Endian" egg-breaking factions as the historical reference for the terms — and explains that the convention only matters when systems with different endianness exchange data.

The processing unit and registers (30:13)

Building on the previously designed ALU, the lecture introduces the register file as fast temporary storage close to the ALU, contrasting it with slow, large main memory. LC-3 has 8 general-purpose registers (R0-R7, 3-bit IDs); MIPS has 32 (r0-r31, 5-bit IDs), which makes MIPS registers cheaper to access but its instruction encodings larger. Register allocation — deciding what lives in registers versus memory — is described as a compiler's job in high-level languages, or the assembly programmer's job otherwise.

The control unit and architectural state (37:21)

The control unit is described as the "conductor" that sequences instruction execution using the instruction register (holds the current instruction's bits) and the program counter (holds the address of the current or next instruction). Together, memory, registers, and the program counter make up the architectural state visible to the programmer. The lecture previews the full LC-3 Von Neumann datapath diagram, pointing out the ALU, register file, instruction register, program counter, control finite state machine, and the tri-state buffer that gates ALU results onto the processor bus.

Instruction formats and encoding (1:07:34)

Every instruction is built from an opcode (what to do) and operands (what to do it to). The lecture hand-encodes an LC-3 ADD instruction (4-bit opcode, three register fields) and a byte-addressable LDR (load register) instruction using base-plus-offset addressing, then contrasts them with the equivalent MIPS R-type (register-register, with an opcode plus function field) and I-type (immediate) encodings, which use more bits for a larger register file and a 16-bit immediate field.

The instruction processing cycle (1:24:47)

The lecture defines the six possible phases of executing an instruction — fetch, decode, evaluate address, fetch operand, execute, store result — and notes that not every instruction needs every phase (ADD skips address evaluation, LDR skips the ALU execute step). It then walks the LC-3 microarchitecture's finite state machine through fetching an instruction (loading the memory address register from the program counter, reading memory into the memory data register, then into the instruction register), decoding it via a 4-to-16 decoder on the opcode bits, and executing ADD and LDR by routing values through the ALU, register file, and processor bus under specific control signals.

Changing the sequence of execution (1:46:05)

The lecture closes with control instructions, which load a new value into the program counter instead of letting it increment sequentially. It shows LC-3's unconditional jump (JMP, register addressing: PC gets the value in a base register) and MIPS's jump (J-type: opcode plus a 26-bit target combined with the top bits of the incremented PC and multiplied by four for word alignment), noting these are what let programs implement branches, function calls, and returns instead of running strictly instruction-after-instruction.

Before you watch

• Be comfortable with the ALU, register, decoder, and finite state machine designs from the digital design portion of the course, since this lecture reuses them directly.
• Review binary and hexadecimal number representation, used throughout for instruction encoding.
• Recall tri-state buffers and bus-based data movement, used to explain how values move between the ALU, memory, and register file on the processor bus.

Check your understanding

1. Why does memory contain no inherent distinction between "instructions" and "data," and what determines how a given bit pattern is interpreted?
2. If a memory is word-addressable with a 16-bit word versus byte-addressable with an 8-bit byte, how does the address needed to reach the same data element change?
3. Why does a big-endian and little-endian system only run into trouble when they communicate with each other, not when each operates on its own?
4. Which phases of the instruction processing cycle does an ADD instruction skip, and which does an LDR (load register) instruction skip? Why?
5. Why do MIPS instructions need more encoding bits for registers than LC-3 instructions, and what tradeoff does that reflect?