Seyed Masoud Hosseini · Overview · Study log · Weekly summaries · Ideas · Search · Transcript · RSS feed

Digital Design & Computer Architecture · Lecture 6 of 37 · 1:23:51

Lecture 4: Finite State Machines, Labs, and Verilog

Study guide

What this lecture covers

This session finishes the course's sequential-logic design unit and answers a concrete question: given a word description of a controller's behavior, how do you turn it into a working finite state machine (FSM) circuit? It reviews why D flip-flops (not transparent latches) are used to build a state register, then designs a Moore FSM traffic-light controller step by step, from state diagram to truth table to Boolean equations to schematic. It closes by comparing state-encoding schemes and Moore vs. Mealy machines, then switches topics to introduce the semester's FPGA labs and the basics of the Verilog hardware description language.

This is a recorded version of the same lecture 4 material, building directly on the previous lecture's coverage of latches, D flip-flops, and combinational logic. After watching, you should be able to build an FSM's state diagram from a specification, derive its next-state and output equations, and explain why a controller needs an explicit reset state.

Key ideas

State register, next-state logic, output logic: the three building blocks of any FSM, where a D flip-flop-based register holds the current state for a full clock cycle so the combinational logic can evaluate.
D flip-flop vs. latch: a flip-flop is edge-triggered (captures data only on the clock edge), while a latch is level-triggered (transparent whenever enabled); FSMs need the former for predictable timing.
Moore FSM: output depends only on the current state, so it can be read directly off the state diagram.
Mealy FSM: output depends on both current state and current input, allowing fewer states but less stable outputs.
Reset state: every FSM needs an explicit reset state, since without one the system's starting behavior is undefined.
State encoding trade-off: binary encoding minimizes flip-flops, one-hot encoding simplifies and automates next-state logic at the cost of more flip-flops, and output encoding (Moore-only) embeds outputs directly in the state bits.
Clock cycle length: must be long enough to accommodate the propagation delay of both the next-state logic and the output logic, or the circuit produces wrong states or outputs.

Walkthrough

Recap: sequential circuits, D flip-flops, and state registers (0:03)

The lecture opens with a review of the previous session: sequential circuits have outputs that depend on both current inputs and stored history, unlike combinational circuits. It revisits the sequential-lock example as an asynchronous state machine, then re-explains why a simple gated D latch is insufficient for a state register, since it is transparent (its output changes whenever the input changes while the clock is high). The fix is the D flip-flop, built from two latches in series, which only captures data on the clock's rising edge and holds it stable for the full cycle. The instructor counts transistors in a four-NAND-gate D flip-flop design (roughly 34 transistors per flip-flop) to contrast with the single transistor used in DRAM, motivating why register storage is comparatively expensive.

Moore vs. Mealy: the two types of FSMs (9:09)

With the state register established, the lecture defines the two FSM types by what determines their output. In a Moore machine, output is a function of the current state alone, so you can read the output directly from which state you're in. In a Mealy machine, output depends on both the current state and the current input, so knowing the state alone is not enough.

Designing the traffic-light Moore FSM (13:13)

Using the textbook's "smart" (but not entirely fair) traffic-light controller as the running example, with two avenues, each with a traffic sensor input and a three-color light output, the lecture builds the state diagram by hand. State S0 (Avenue A green, Avenue B red) holds while traffic sensor TA is true, moves to intermediate state S1 (yellow) once traffic clears, then unconditionally to S2 (A red, B green), through yellow state S3, and back to S0. Because the lights shown are drawn inside each state circle rather than on the transition arrows, this is confirmed as a Moore machine. The design deliberately does not enforce fairness: an avenue with continuous traffic stays green indefinitely, illustrating a scheduling trade-off relevant to hardware controllers generally.

From state diagram to truth-table equations and timing (17:17)

The state diagram is converted into a compressed truth table with don't-care entries, then the four states are encoded as two bits. From the encoded table, next-state equations are derived in sum-of-products form; one of them simplifies via the uniting theorem to S1 XOR S0. The same approach produces the two-bit output equations for the two lights, which, because this is a Moore machine, depend only on the state bits, not on the traffic sensor inputs. A timing diagram is then used to show how an asynchronous reset and gate propagation delays affect when the state register and outputs actually settle, and the lecture notes that the clock period must be long enough to cover the slowest combinational path or the circuit will latch the wrong state.

State encoding: binary, one-hot, and output encoding (29:28)

Returning to the four-state traffic light, the lecture compares three ways to assign bit patterns to states. Binary (fully encoded) uses the minimum log2(states) bits, minimizing flip-flops but not necessarily simplifying the logic. One-hot encoding uses one bit per state, which is easy to automate and simplifies next-state logic at the cost of more flip-flops. Output encoding, usable only for Moore machines, assigns state bits to directly match the output signals (one bit per light color), which removes the need for separate output logic. The lecture stresses this is a designer trade-off among flip-flop count, logic complexity, and other constraints, especially significant in circuits with very large numbers of states.

Moore vs. Mealy trade-offs via the smiling-snail example (33:31)

A second textbook example, a snail whose brain should output a "smile" signal after detecting the bit pattern 1101, is modeled first as a five-state Moore machine (smile is an output only in the final state) and then as a four-state Mealy machine (smile is output on a transition rather than requiring an extra state). This shows concretely how a Mealy design can use fewer states in exchange for output logic that reacts to inputs rather than state alone. The lecture closes the FSM design topic by generalizing the design procedure: enumerate states from a specification, build the state diagram, always include a reset state, and note that real hardware systems typically use many communicating FSMs, rather than one enormous state machine.

Lab sequence, FPGA architecture, and first Verilog module (40:36)

The lecture then shifts to logistics for the ten-lab FPGA sequence (30 of 100 course points, worked in pairs on Basys 3 boards), previewing each lab from a basic comparator circuit through an adder, seven-segment display, a turn-signal FSM, an ALU and its testbench, MIPS assembly, a two-part processor integration, and a final performance-improvement lab. Research examples using the group's DRAM-Bender FPGA infrastructure (RowHammer, RowPress, DRAM computation studies) illustrate real uses of FPGAs beyond the course. The lecture then explains FPGA internals (lookup tables, switch boxes, I/O blocks, and the synthesis/placement/routing/bitstream CAD flow using Xilinx Vivado), and, motivated by transistor counts in modern chips reaching over 100 billion, introduces Verilog as a hardware description language. It ends with the syntax for defining a Verilog module, its input/output ports, and bit-range notation such as [31:0] A for multi-bit signals.

Before you watch

Review the prior lecture's coverage of latches versus D flip-flops, since this lecture opens by building directly on that distinction.
Be comfortable with Boolean sum-of-products simplification, including don't-care terms, since the FSM equations rely on it.

Check your understanding

Why is a transparent D latch unsuitable for building the state register of a synchronous FSM?
In the traffic-light example, why must the reset state be explicitly defined rather than left implicit?
What trade-off does one-hot encoding make compared to binary encoding of FSM states?
Why does the Mealy version of the snail FSM need one fewer state than the Moore version?
Why must the clock cycle be long enough to cover the delay of both the next-state logic and the output logic?

Vocabulary

finite state machine (FSM) (noun): A circuit that moves between a fixed number of states based on rules, one state at a time.
We design a traffic-light controller as a finite state machine.
sequential logic (noun): A type of circuit whose output depends on stored history, not just current inputs.
Sequential logic needs memory to remember the past state.
state register (noun): A group of flip-flops that stores the FSM's current state for one clock cycle.
The state register holds the current traffic-light state.
flip-flop (noun): A memory circuit that captures and holds one bit of data only at the clock edge.
The FSM's state register is built from D flip-flops.
latch (noun): A memory circuit whose output can change any time its enable signal is on, not just at a clock edge.
A latch is transparent, so it is not used for the state register.
edge-triggered (adjective): Reacting only at the exact moment the clock signal changes, not the whole time it is high.
A flip-flop is edge-triggered, unlike a level-triggered latch.
level-triggered (adjective): Reacting the whole time a control signal stays at a certain value (like high), not just at one instant.
A latch is level-triggered, so its output can keep changing.
transparent (adjective): Describes a circuit whose output copies its input continuously while enabled.
A latch is transparent whenever its clock input is high.
Moore machine (noun): An FSM whose output depends only on the current state, not the current input.
The traffic-light controller is designed as a Moore machine.
Mealy machine (noun): An FSM whose output depends on both the current state and the current input.
A Mealy machine can use fewer states than an equivalent Moore machine.
state diagram (noun): A drawing that shows an FSM's states as circles and its transitions as arrows.
We build the state diagram before writing any equations.
state encoding (noun): The choice of which bit pattern represents each state of an FSM.
Binary and one-hot are two common state encoding schemes.
one-hot encoding (noun): A state encoding where exactly one bit is set to 1 for each state, using one flip-flop per state.
One-hot encoding uses more flip-flops but simpler next-state logic.
sum-of-products (noun): A way of writing a Boolean equation as several AND terms added together with OR.
We write the next-state logic in sum-of-products form.
don't-care entry (noun): A place in a truth table where the output can be either 0 or 1, because that input case never happens.
The unused state codes are marked as don't-care entries.
uniting theorem (noun): A Boolean algebra rule that combines two similar terms differing in only one variable into a simpler term.
The equation simplifies using the uniting theorem to S1 XOR S0.
propagation delay (noun): The time a signal takes to finish changing after its input changes.
The clock period must be longer than the logic's propagation delay.
timing diagram (noun): A drawing that shows how signals change over time, lined up on the same time axis.
The timing diagram shows when the state register settles after reset.
asynchronous (adjective): Happening without being controlled by a shared clock signal.
The reset signal here acts asynchronously on the flip-flops.
reset state (noun): The known starting state an FSM enters when it is turned on or reset.
Every FSM design needs an explicit reset state.
trade-off (noun): A balance where gaining one benefit means giving up another.
Choosing an encoding scheme is a trade-off between flip-flop count and logic complexity.
output encoding (noun): A state encoding, usable only in Moore machines, where the state bits are the same as the output bits.
Output encoding removes the need for separate output logic.
transistor (noun): The basic tiny switch used to build all digital circuits.
A D flip-flop needs roughly 34 transistors to build.
DRAM (noun): A type of memory chip that stores each bit using a single transistor and capacitor.
DRAM uses far fewer transistors per bit than a flip-flop register.
FPGA (noun): A chip whose internal circuit can be reprogrammed after manufacturing to implement different designs.
The course labs run on FPGA boards.
lookup table (noun): A small memory inside an FPGA that stores the answer for every possible input combination.
An FPGA implements logic functions using lookup tables.
synthesis (noun): The process of turning a hardware description into an actual gate-level circuit.
Vivado performs synthesis, placement, and routing on the design.
Verilog (noun): A language used to describe digital hardware circuits in text form.
We introduce Verilog to describe the FSM in code.
hardware description language (noun): A programming-like language used to describe the structure and behavior of digital circuits.
Verilog is one common hardware description language.
module (noun): In Verilog, a named block of code that describes one circuit with defined inputs and outputs.
Every Verilog design starts by defining a module.
port (noun): An input or output connection point on a hardware module.
The module's ports are listed inside the parentheses.
bit-range notation (phrase): A way of naming a group of bits within a wider signal, like [31:0].
The 32-bit input is declared using bit-range notation [31:0] A.
fairness (noun): A design property where every user or input gets a reasonable, equal chance of being served.
The traffic-light design does not guarantee fairness between the two avenues.
combinational logic (noun): A circuit whose output depends only on its current inputs, with no memory of the past.
The next-state logic is built from combinational logic.
truth table (noun): A table listing every possible input combination and the resulting output.
We build a truth table for the next-state equations.

From the YouTube description

Digital Design and Computer Architecture, ETH Zürich, Spring 2025 (https://safari.ethz.ch/ddca/spring2025/)

Lecture 4d: Sequential Logic II, Labs, Verilog (Premiere)
Lecturer: Prof. Onur Mutlu
Date: 28 February 2025

Lecture 4a Slides (pptx): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture4a-sequential-logic-ii-beforelecture.pptx
Lecture 4a Slides (pdf): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture4a-sequential-logic-ii-beforelecture.pdf

Lecture 4b Slides (pptx): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture4b-labs-fpgas.pptx
Lecture 4b Slides (pdf): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture4b-labs-fpgas.pdf

Lecture 4c Slides (pptx): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture4c-hdl-verilog-beforelecture.pptx
Lecture 4c Slides (pdf): https://safari.ethz.ch/ddca/spring2025/lib/exe/fetch.php?media=onur-ddca-2025-lecture4c-hdl-verilog-beforelecture.pdf

Recommended Reading:
====================
A Modern Primer on Processing in Memory
https://arxiv.org/abs/2012.03112

Intelligent Architectures for Intelligent Computing Systems
https://arxiv.org/abs/2012.12381

RowHammer: A Retrospective
https://people.inf.ethz.ch/omutlu/pub/RowHammer-Retrospective_ieee_tcad19.pdf

Fundamentally Understanding and Solving RowHammer
https://arxiv.org/abs/2211.07613

RECOMMENDED LECTURE VIDEOS & PLAYLISTS:
========================================
Computer Architecture Fall 2021 Lectures Playlist:
https://www.youtube.com/watch?v=4yfkM_5EFgo&list=PL5Q2soXY2Zi-Mnk1PxjEIG32HAGILkTOF

Digital Design and Computer Architecture Spring 2021 Livestream Lectures Playlist:
https://www.youtube.com/watch?v=LbC0EZY8yw4&list=PL5Q2soXY2Zi_uej3aY39YB5pfW4SJ7LlN

Featured Lectures:
https://www.youtube.com/watch?v=jVYCchBGNVc&list=PL5Q2soXY2Zi8VrmOTz44l2WupethSdh-M&index=1

Interview with Professor Onur Mutlu:
https://www.youtube.com/watch?v=8ffSEKZhmvo&list=PL5Q2soXY2Zi8VrmOTz44l2WupethSdh-M&index=9

The Story of RowHammer Lecture:
https://www.youtube.com/watch?v=sgd7PHQQ1AI&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=39

Accelerating Genome Analysis Lecture:
https://www.youtube.com/watch?v=r7sn41lH-4A&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=41

Memory-Centric Computing Systems Tutorial at IEDM 2021:
https://www.youtube.com/watch?v=H3sEaINPBOE&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=35

Intelligent Architectures for Intelligent Machines Lecture:
https://www.youtube.com/watch?v=GTieZPY4Wmc&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=38

Computer Architecture Fall 2020 Lectures Playlist:
https://www.youtube.com/watch?v=c3mPdZA-Fmc&list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN

Digital Design and Computer Architecture Spring 2020 Lectures Playlist:
https://www.youtube.com/watch?v=AJBmIaUneB0&list=PL5Q2soXY2Zi_FRrloMa2fUYWPGiZUBQo2

Public Lectures by Onur Mutlu, Playlist:
https://www.youtube.com/watch?v=kgiZlSOcGFM&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl

Computer Architecture at Carnegie Mellon Spring 2015 Lectures Playlist:
https://www.youtube.com/watch?v=zLP_X4wyHbY&list=PL5PHm2jkkXmi5CxxI7b3JCL1TWybTDtKq

Rethinking Memory System Design Lecture @stanfordonline :
https://www.youtube.com/watch?v=F7xZLNMIY1E&list=PL5Q2soXY2Zi8D_5MGV6EnXEJHnV2YFBJl&index=4

← Lecture 4: Sequential Logic II, Labs, and Verilog · Lecture 5: HDL, Verilog II, Timing and Verification →