Lecture 4: Finite State Machines, Labs, and Verilog

What this lecture covers

This session finishes the course's sequential-logic design unit and answers a concrete question: given a word description of a controller's behavior, how do you turn it into a working finite state machine (FSM) circuit? It reviews why D flip-flops (not transparent latches) are used to build a state register, then designs a Moore FSM traffic-light controller step by step, from state diagram to truth table to Boolean equations to schematic. It closes by comparing state-encoding schemes and Moore vs. Mealy machines, then switches topics to introduce the semester's FPGA labs and the basics of the Verilog hardware description language.

This is a recorded version of the same lecture 4 material, building directly on the previous lecture's coverage of latches, D flip-flops, and combinational logic. After watching, you should be able to build an FSM's state diagram from a specification, derive its next-state and output equations, and explain why a controller needs an explicit reset state.

Key ideas

• State register, next-state logic, output logic: the three building blocks of any FSM, where a D flip-flop-based register holds the current state for a full clock cycle so the combinational logic can evaluate.
• D flip-flop vs. latch: a flip-flop is edge-triggered (captures data only on the clock edge), while a latch is level-triggered (transparent whenever enabled); FSMs need the former for predictable timing.
• Moore FSM: output depends only on the current state, so it can be read directly off the state diagram.
• Mealy FSM: output depends on both current state and current input, allowing fewer states but less stable outputs.
• Reset state: every FSM needs an explicit reset state, since without one the system's starting behavior is undefined.
• State encoding trade-off: binary encoding minimizes flip-flops, one-hot encoding simplifies and automates next-state logic at the cost of more flip-flops, and output encoding (Moore-only) embeds outputs directly in the state bits.
• Clock cycle length: must be long enough to accommodate the propagation delay of both the next-state logic and the output logic, or the circuit produces wrong states or outputs.

Walkthrough

Recap: sequential circuits, D flip-flops, and state registers (0:03)

The lecture opens with a review of the previous session: sequential circuits have outputs that depend on both current inputs and stored history, unlike combinational circuits. It revisits the sequential-lock example as an asynchronous state machine, then re-explains why a simple gated D latch is insufficient for a state register, since it is transparent (its output changes whenever the input changes while the clock is high). The fix is the D flip-flop, built from two latches in series, which only captures data on the clock's rising edge and holds it stable for the full cycle. The instructor counts transistors in a four-NAND-gate D flip-flop design (roughly 34 transistors per flip-flop) to contrast with the single transistor used in DRAM, motivating why register storage is comparatively expensive.

Moore vs. Mealy: the two types of FSMs (9:09)

With the state register established, the lecture defines the two FSM types by what determines their output. In a Moore machine, output is a function of the current state alone, so you can read the output directly from which state you're in. In a Mealy machine, output depends on both the current state and the current input, so knowing the state alone is not enough.

Designing the traffic-light Moore FSM (13:13)

Using the textbook's "smart" (but not entirely fair) traffic-light controller as the running example, with two avenues, each with a traffic sensor input and a three-color light output, the lecture builds the state diagram by hand. State S0 (Avenue A green, Avenue B red) holds while traffic sensor TA is true, moves to intermediate state S1 (yellow) once traffic clears, then unconditionally to S2 (A red, B green), through yellow state S3, and back to S0. Because the lights shown are drawn inside each state circle rather than on the transition arrows, this is confirmed as a Moore machine. The design deliberately does not enforce fairness: an avenue with continuous traffic stays green indefinitely, illustrating a scheduling trade-off relevant to hardware controllers generally.

From state diagram to truth-table equations and timing (17:17)

The state diagram is converted into a compressed truth table with don't-care entries, then the four states are encoded as two bits. From the encoded table, next-state equations are derived in sum-of-products form; one of them simplifies via the uniting theorem to S1 XOR S0. The same approach produces the two-bit output equations for the two lights, which, because this is a Moore machine, depend only on the state bits, not on the traffic sensor inputs. A timing diagram is then used to show how an asynchronous reset and gate propagation delays affect when the state register and outputs actually settle, and the lecture notes that the clock period must be long enough to cover the slowest combinational path or the circuit will latch the wrong state.

State encoding: binary, one-hot, and output encoding (29:28)

Returning to the four-state traffic light, the lecture compares three ways to assign bit patterns to states. Binary (fully encoded) uses the minimum log2(states) bits, minimizing flip-flops but not necessarily simplifying the logic. One-hot encoding uses one bit per state, which is easy to automate and simplifies next-state logic at the cost of more flip-flops. Output encoding, usable only for Moore machines, assigns state bits to directly match the output signals (one bit per light color), which removes the need for separate output logic. The lecture stresses this is a designer trade-off among flip-flop count, logic complexity, and other constraints, especially significant in circuits with very large numbers of states.

Moore vs. Mealy trade-offs via the smiling-snail example (33:31)

A second textbook example, a snail whose brain should output a "smile" signal after detecting the bit pattern 1101, is modeled first as a five-state Moore machine (smile is an output only in the final state) and then as a four-state Mealy machine (smile is output on a transition rather than requiring an extra state). This shows concretely how a Mealy design can use fewer states in exchange for output logic that reacts to inputs rather than state alone. The lecture closes the FSM design topic by generalizing the design procedure: enumerate states from a specification, build the state diagram, always include a reset state, and note that real hardware systems typically use many communicating FSMs, rather than one enormous state machine.

Lab sequence, FPGA architecture, and first Verilog module (40:36)

The lecture then shifts to logistics for the ten-lab FPGA sequence (30 of 100 course points, worked in pairs on Basys 3 boards), previewing each lab from a basic comparator circuit through an adder, seven-segment display, a turn-signal FSM, an ALU and its testbench, MIPS assembly, a two-part processor integration, and a final performance-improvement lab. Research examples using the group's DRAM-Bender FPGA infrastructure (RowHammer, RowPress, DRAM computation studies) illustrate real uses of FPGAs beyond the course. The lecture then explains FPGA internals (lookup tables, switch boxes, I/O blocks, and the synthesis/placement/routing/bitstream CAD flow using Xilinx Vivado), and, motivated by transistor counts in modern chips reaching over 100 billion, introduces Verilog as a hardware description language. It ends with the syntax for defining a Verilog module, its input/output ports, and bit-range notation such as [31:0] A for multi-bit signals.

Before you watch

• Review the prior lecture's coverage of latches versus D flip-flops, since this lecture opens by building directly on that distinction.
• Be comfortable with Boolean sum-of-products simplification, including don't-care terms, since the FSM equations rely on it.

Check your understanding

1. Why is a transparent D latch unsuitable for building the state register of a synchronous FSM?
2. In the traffic-light example, why must the reset state be explicitly defined rather than left implicit?
3. What trade-off does one-hot encoding make compared to binary encoding of FSM states?
4. Why does the Mealy version of the snail FSM need one fewer state than the Moore version?
5. Why must the clock cycle be long enough to cover the delay of both the next-state logic and the output logic?