Lecture 8: Instruction Set Architectures II

What this lecture covers

This lecture continues directly from the Von Neumann model lecture, first recapping the instruction processing cycle and the LC-3 finite state machine, then spending most of its time on how an instruction set architecture (ISA) is actually designed: what opcodes to include, what data types to support, and what addressing modes to offer. It compares LC-3 (a simple, educational ISA) against MIPS (a real, reduced instruction set) throughout to make the underlying trade-offs concrete.

After watching, you'll be able to explain the "semantic gap" concept and how it relates to hardware versus software complexity, read and hand-decode LC-3 immediate, PC-relative, indirect, and base-plus-offset addressing modes, and explain why LC-3 uses condition codes for branching while MIPS uses direct register comparison.

Key ideas

• Instruction set architecture (ISA): the interface between software and hardware, specifying memory organization, registers, and the instruction set (opcodes, data types, addressing modes, encoding).
• Semantic gap: how close an ISA's instructions and data types are to high-level language constructs; complex instructions/data types mean a small semantic gap (easier for software, harder for hardware); simple ones mean a large gap (easier for hardware, harder for software).
• Opcode trade-offs: more, more powerful opcodes reduce code size and ease compiler mapping but increase hardware complexity; fewer, simpler opcodes (as in reduced instruction set computers like MIPS) keep hardware simple but require more instructions per task.
• Steering bit: a bit within an opcode's remaining fields (for example bit 5 in LC-3's ADD/AND) that selects between two interpretations of an instruction, such as register operand versus immediate operand.
• Addressing modes: mechanisms for locating an operand — immediate, register, PC-relative, indirect, and base-plus-offset are covered, each with different reach and hardware cost.
• Indirect addressing: an addressing mode (LC-3's LDI/STI, absent in MIPS) that reads a memory location to get an address, then reads again at that address — useful for pointer-based data structures.
• Condition codes vs. compare-and-branch: LC-3 sets N/Z/P (negative/zero/positive) bits on every register write and branches based on them; MIPS instead compares two registers directly in a single branch instruction (BEQ), trading more hardware complexity for fewer instructions.

Walkthrough

Recap: instruction cycle and jump (6:46)

The lecture reviews the Von Neumann model's two hallmarks (stored program, sequential processing), the instruction processing cycle (fetch, decode, evaluate address, fetch operand, execute, store result), and how the same memory value is interpreted as an instruction or data depending on which cycle stage reads it. It walks back through the LC-3 unconditional jump instruction and its finite state machine implementation, where a source register's value is loaded directly into the program counter.

What an ISA specifies, and opcode trade-offs (18:51)

The lecture formally defines an ISA as the interface specifying memory organization, register count, and the instruction set. It contrasts small opcode sets (simpler hardware, the reduced instruction set computer philosophy behind MIPS) against large or complex opcode sets (examples include a multiply-accumulate opcode and a VAX instruction that saved an entire program's state), and frames the core trade-off as hardware complexity versus software complexity and instruction latency.

Data types and the semantic gap (26:55)

LC-3 supports only two's complement integers; MIPS adds unsigned integers and floating point. The lecture defines two's complement (negate by bitwise NOT plus one) and introduces the semantic gap concept using examples like hypothetical doubly-linked-list or hash-map instructions (small gap, more hardware work) versus primitive add/shift-only instructions (large gap, more software work). A binary-coded decimal example illustrates how a data type's usefulness depends on how well it matches the way data is naturally represented.

Addressing modes overview (41:05)

Addressing mode is defined as the mechanism for locating an operand. LC-3 supports immediate, register, and three memory addressing modes (PC-relative, indirect, base-plus-offset); MIPS supports fewer modes (base-plus-offset, immediate, pseudo-direct for jumps) but no indirect mode. The lecture repeats the same hardware-versus-software trade-off pattern seen with opcodes and data types.

Immediate operands and instruction complexity (47:09)

Using LC-3's steering bit (bit 5) on ADD/AND, the lecture shows how the same opcode can operate on either two registers or a register plus a 5-bit sign-extended immediate, saving a register when adding or subtracting small constants. It then uses subtraction as a running example: MIPS has a dedicated subtract instruction, while LC-3 (lacking one) computes it as two's complement negation followed by addition, needing more instructions but simpler control logic — illustrating the complex-vs-simple-instruction trade-off concretely.

Data movement and addressing modes in practice (1:10:14)

The lecture works through LC-3's PC-relative load/store (limited to addresses within about 256 words of the instruction), indirect load/store (two memory accesses, useful for pointer chasing through linked structures, not present in MIPS due to its simplicity philosophy), and base-plus-offset load/store (shared conceptually with MIPS's LW/SW). It also covers register-initialization addressing: LC-3's load-effective-address (LEA, PC-relative but skips the memory access) and MIPS's load-upper-immediate (LUI, sets a register's upper 16 bits for building 32-bit constants without touching memory).

Conditional branches: condition codes vs. direct comparison (1:36:31)

LC-3 (like x86) sets three single-bit condition-code registers (N, Z, P) on every general-purpose register write, and a branch instruction tests one or more of these bits — testing all three yields an unconditional branch, testing none yields a no-op. MIPS instead uses BEQ, which directly compares two registers and branches if they're equal, requiring more comparison hardware but replacing what would take four LC-3 instructions (subtract via negation, then test the zero condition code) with a single instruction.

Before you watch

• Watch the previous lecture in this course on the Von Neumann model and LC-3/MIPS instruction encoding, since this lecture builds directly on the fetch-decode-execute cycle and the ADD/LDR examples introduced there.
• Be comfortable with two's complement binary representation and sign extension.
• Review the LC-3 datapath (register file, ALU, memory address/data registers, program counter) from the prior lecture, since new addressing-mode hardware is added onto it here.

Check your understanding

1. What does the "semantic gap" measure, and how do complex versus simple instructions trade off hardware complexity against software complexity?
2. How does LC-3's steering bit let the same ADD opcode operate on either two registers or a register and an immediate value?
3. Why is LC-3's indirect addressing mode useful for pointer-based data structures, and why doesn't MIPS include it?
4. Explain how LC-3 implements the equivalent of MIPS's BEQ using condition codes, and why MIPS's approach needs fewer instructions but more comparison hardware.
5. Why is LC-3's PC-relative addressing mode limited in the memory range it can reach, and what alternative addressing mode avoids that limitation?