Lecture 13: Digital Circuit Speed and RC Delay

What this lecture covers

Picking up from the previous lecture's RC circuit foundations, this lecture answers the question raised by the two-inverter demo: how do you actually compute the delay of a digital circuit? It introduces an intuitive, calculus-free way to sketch RC step responses ("Practice it Like Perreault"), then applies it to compute the rising and falling delay of an inverter driving another inverter's gate capacitance, using Thevenin equivalents to simplify the falling-delay case. It closes with a real-world demo of crosstalk between adjacent chip pins caused by parasitic capacitance.

After watching, you can sketch an RC step response by inspection (initial value, final value, and rise or decay form), compute an inverter's rising delay tR and falling delay tF from RL, RON, and gate capacitance CGS, and explain why an RC time constant is a fast way to estimate circuit delay without solving a differential equation.

Key ideas

• Two RC waveform forms: any step-driven RC circuit is either V0 + (VI - V0)(1 - e^{-t/RC}) (rising toward a higher final value) or V0 - (V0 - VI)e^{-t/RC} written equivalently as final value plus a decaying difference (falling toward a lower final value).
• Intuitive sketching ("Practice it Like Perreault"): read off the initial value and the final (steady-state, open-circuit) value directly from the circuit, then write down the exponential form connecting them — no differential equation needed.
• Capacitor as open circuit in steady state: after a long time under DC excitation, a capacitor draws no current, so its voltage settles to whatever a simple resistive (or Thevenin) analysis predicts.
• Rising delay tR: the time for an inverter's output node to rise from its low value to a defined logical-one threshold VOH, computed from the RC step response of the load capacitance charging through RL.
• Falling delay tF: the time to fall to a defined logical-zero threshold VOL, computed using a Thevenin equivalent (RTH = RL || RON, VTH from the voltage divider) for the resistive network around the capacitor.
• RC time constant as a delay estimator: the product of the driving resistance and the load capacitance gives a quick order-of-magnitude estimate of circuit delay, even before computing exact rise/fall times.
• Crosstalk: a parasitic capacitance between adjacent conductors (e.g., chip pins) couples a fast transition on one line into unwanted voltage spikes on a neighboring line; slowing down transitions reduces this coupling.

Walkthrough

Review: exponential rise and decay forms, and intuitive sketching (0:06)

The lecture reviews the two waveform shapes that arise from a step-driven RC circuit — rising toward a larger final value or decaying toward a smaller one, both governed by the time constant RC — and then introduces an intuitive method for sketching either shape directly from the circuit: identify the initial value (from the given initial condition), identify the final value (by treating the capacitor as an open circuit under the DC steady state), and write down the appropriate exponential form connecting the two, without solving a differential equation.

The exponential-decay case worked by inspection (15:03)

The intuitive method is applied to the case where the input VI is smaller than the initial capacitor voltage VO, producing a decaying waveform of the form VI + (VO - VI)e^{-t/RC}. The lecture emphasizes that both forms (rising and decaying) share the same time constant RC and can be written down by inspection once the initial and final values are known.

Setting up the inverter delay problem (18:40)

The lecture returns to the two-inverter demo from the previous lecture and draws the internal equivalent circuit: an inverter's gate capacitance CGS charging or discharging through the driving inverter's load resistor RL (and, when the driving transistor is on, its on-resistance RON). This sets up the calculation of both a rising delay tR and a falling delay tF for the node between the two inverters.

Defining and computing rising delay (21:12)

Rising delay tR is defined as the time for the output node to rise from near zero to a valid logical-one voltage VOH. Using the intuitive method, the node starts at approximately zero and rises toward VS in the 1 - e^{-t/RC} form; solving VOH = VS(1 - e^{-tR/RC}) for tR gives tR = -RL*CGS*ln(1 - VOH/VS). With example numbers (RL = 1kOhm, VS = 5V, VOH = 4V, CGS = 0.1pF), this works out to about 0.16 nanoseconds, and the lecture notes chip designers perform this same calculation for essentially every subcircuit.

Falling delay and the Thevenin shortcut (32:46)

For the falling transition, the node starts at VS and falls as the driving transistor turns on and pulls current through RON to ground while RL still connects to VS. Because the resistive network around the capacitor is now more complex, the lecture reduces it to a Thevenin equivalent to find the final value by inspection.

Finding the Thevenin resistance and voltage-divider final value (37:16)

The Thevenin resistance seen by the capacitor is RL in parallel with RON, and the Thevenin voltage (the open-circuit voltage with the capacitor removed) is given by the familiar voltage-divider expression VS*RON/(RL + RON). With initial value VS and final value VTH, the falling waveform is sketched immediately as VTH + (VS - VTH)e^{-t/(RTH*CGS)}, and solving for when this reaches VOL gives the falling delay tF.

Why the RC time constant itself matters (45:43)

After computing example rising and falling delays (about 0.16 ns and 1.6 ps for two different parameter sets), the lecture highlights that the plain RC time constant of each circuit (about 0.1 ns and 1 ps respectively) is itself a good quick estimate of the expected delay — useful for a fast, order-of-magnitude sanity check without working through the full exponential expression.

Parasitic capacitance and crosstalk between pins (51:17)

The lecture recounts a real chip design problem: shrinking RL and RON to speed up transitions instead produced unexpected voltage spikes on a neighboring, supposedly quiet, pin. A demo models two adjacent wires and shows that moving them apart removes the spikes, revealing a parasitic capacitance between the pins as the cause (crosstalk). Since pins cannot be spaced far apart in a real chip, the fix demonstrated is to slow down the driving transition (e.g., using a triangular rather than square input), which reduces the coupled spikes.

Before you watch

• Review the RC differential equation and its particular-plus-homogeneous solution from the previous lecture (Lec 12).
• Be comfortable with Thevenin equivalents, voltage dividers, and parallel resistance combinations.
• Recall the concept of gate capacitance CGS and why it arises inside a MOSFET.

Check your understanding

1. How does the "Practice it Like Perreault" method let you sketch an RC step response without solving a differential equation?
2. Why does a capacitor behave like an open circuit after a long time under a DC input?
3. What roles do RL and RON each play in the rising delay versus the falling delay of an inverter?
4. Why is the Thevenin equivalent useful for finding the final value of the falling-delay waveform?
5. What causes the voltage spikes observed on a neighboring pin, and why does slowing the driving transition reduce them?