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Embedded Systems, 6502 breadboard computer · Lecture 7 of 29 · 17:42

Part 7: Subroutine calls, now with RAM

Subroutine calls, now with RAM — 6502 part 7 on YouTube

Study guide

What this lecture covers

This video completes the RAM wiring started in part 6 by adding the timing logic needed so the RAM chip's chip-select signal only goes active once the address lines have stabilized, and goes inactive again before they change on the next cycle. With that logic connected, the "Hello world" program that relies on subroutine calls finally works.

The lecture then reconnects the Arduino bus monitor to single-step through a JSR/RTS sequence and confirm, cycle by cycle, that the return address is correctly pushed to and pulled from the stack in RAM. It closes by adding a clear-display instruction to the LCD program so the screen resets cleanly, and previews replacing the manual clock module with a real crystal oscillator in the next video.

Key ideas

  • Chip-select timing logic: extra NAND-gate logic ensures the RAM's chip-select signal activates only after the address bus is stable and deactivates before the address changes, avoiding corrupted reads or writes.
  • Reusing existing gates: the same inverted A15 signal already used for the EEPROM's chip select is fed into another NAND gate along with the clock signal to generate the RAM's properly timed chip select.
  • Unused gate inputs: leaving logic-chip inputs unconnected risks them floating and causing noise, so the lecture ties the unused fourth NAND gate's inputs high as good practice.
  • Stack push/pull verified on the bus: single-stepping shows the processor writing the return address to $01FF/$01FE during JSR and correctly reading it back during RTS, something that failed entirely before RAM was installed.
  • Internal-only clock cycles: some clock cycles during JSR/RTS don't actually transfer meaningful bus data; the address and data lines just happen to show whatever was last driven, which can be misleading when reading a bus trace.
  • Clear display instruction: sending an all-zero-except-last-bit instruction byte to the LCD clears its screen, useful for resetting cleanly instead of relying on the display's power-on blank state.

Walkthrough

Completing the RAM chip-select logic (0:00)

Building on part 6's partial RAM wiring, address line 14 is connected to the RAM's output enable pin, and the already-inverted A15 signal is combined with the clock signal through another NAND gate to drive the RAM's properly timed chip select.

Powering up and confirming the fix (4:02)

With the wiring complete, the unmodified subroutine-based program from part 5 is run again. This time it works, printing text to the LCD instead of failing, confirming that the missing RAM was indeed the root cause.

Single-stepping the working stack (6:04)

The Arduino bus monitor is reconnected to trace a full JSR call to the LCD-instruction subroutine and its matching RTS, showing the return address correctly written to and read back from $01FF/$01FE, in contrast to the broken behavior seen without RAM in part 5.

Adding a clear-display instruction (13:12)

Noting that resetting no longer clears a previously used LCD, the lecture looks up the LCD's clear-display instruction in the datasheet and adds it as another subroutine call at the start of the program, then reassembles and reprograms the EEPROM to confirm the screen clears properly on reset.

Before you watch

  • Watch part 5 (the stack failure) and part 6 (the initial RAM wiring) first, since this video directly resolves the problem they set up.
  • Familiarity with reading a single-stepped address/data bus trace, introduced in earlier videos, is assumed.

Check your understanding

  1. Why does the RAM's chip-select signal need extra timing logic instead of being driven directly by the address lines?
  2. What evidence in the bus trace confirms that the return address is now being correctly saved to and restored from the stack?
  3. Why can some values seen on the bus during certain clock cycles be misleading when tracing JSR and RTS?
  4. What instruction byte clears the LCD display, and why did the lecture add it to the initialization sequence?
  5. What change does the lecture plan for the next video regarding the computer's clock source?

Vocabulary

chip-select timing (noun)
The precise control of when a chip's enable signal turns on and off.
Chip-select timing ensures the RAM only activates at the right moment.
NAND gate (noun)
A basic logic circuit that outputs false only when both its inputs are true.
A NAND gate combines the address and clock signals for timing.
stabilize (verb)
To settle into a steady, unchanging state.
The chip-select signal waits until the address lines stabilize.
floating input (noun)
An unconnected input pin whose value is unpredictable and can pick up noise.
A floating input on an unused gate can cause unwanted noise.
output enable (noun)
A pin that controls whether a chip is allowed to output data onto the bus.
Address line 14 connects to the RAM's output enable pin.
bus trace (noun)
A recorded sequence of values seen on a processor's address and data lines.
The bus trace shows the return address being saved correctly.
internal-only cycle (phrase)
A clock cycle where the processor does internal work without transferring real bus data.
Some internal-only cycles can look confusing on a bus trace.
root cause (noun)
The true underlying reason behind an observed problem.
Missing RAM was confirmed as the root cause of the earlier failure.
initialization sequence (noun)
The fixed series of setup steps run before normal operation begins.
A clear-display instruction is added to the initialization sequence.
crystal oscillator (noun)
A component that produces a very stable, precise repeating electrical signal.
The next video will replace the manual clock with a crystal oscillator.
complete (verb)
To finish something that was started earlier.
This video completes the RAM wiring started previously.
deactivate (verb)
To turn something off or make it inactive.
The chip select must deactivate before the address changes.
confirm (verb)
To show that something is true or correct.
The bus trace confirms the fix worked.
reprogram (verb)
To load new instructions or data onto a memory chip.
The EEPROM is reprogrammed to add the clear-display step.
power-on state (noun)
The initial condition a device is in right after being turned on.
The LCD's power-on state leaves the screen blank.
good practice (noun)
A recommended way of doing something that avoids common problems.
Tying unused inputs high is good practice.
logic chip (noun)
A chip built from basic gates like AND, OR, and NAND.
A logic chip combines the address and clock signals.
resolve (verb)
To fix or settle a problem.
Adding the timing logic resolves the earlier failure.
verify (verb)
To check that something is working as expected.
Single-stepping helps verify the stack push and pull.
unmodified (adjective)
Left exactly the same, without any changes.
The unmodified program from before is run again to test the fix.

Chapters

From the YouTube description

Schematics, kits, and more: https://eater.net/6502

Part 1: https://www.youtube.com/watch?v=LnzuMJLZRdU
Part 2: https://www.youtube.com/watch?v=yl8vPW5hydQ
Part 3: https://www.youtube.com/watch?v=oO8_2JJV0B4
Part 4: https://www.youtube.com/watch?v=FY3zTUaykVo
Part 5: https://www.youtube.com/watch?v=xBjQVxVxOxc
Part 6: https://www.youtube.com/watch?v=i_wrxBdXTgM
Part 7: This video!

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