Lecture 21: RS232 Interface With the 6551 UART

What this lecture covers

The lecture moves the breadboard 6502 computer's serial interface from software-timed bit-banging to dedicated hardware: the 6551 Asynchronous Communications Interface Adapter (ACIA), a UART. It follows directly from the earlier videos that built RS-232 transmit and receive routines entirely in software.

By the end, you can explain why a UART frees the CPU from precise bit timing, how the 6551 connects to the RS-232 line through the MAX232 charge-pump chip covered previously, and how the address bus and chip-select logic route CPU reads and writes to a new device sharing the data bus with ROM, RAM, and the existing VIA.

Key ideas

• Why a UART: bit-banged serial code had to hit exactly 104 microseconds per bit and blocked the CPU from doing anything else while sending or receiving; a UART handles bit timing in hardware and exposes whole bytes to the CPU.
• 6551 ACIA registers: a data register (read receiver data / write transmitter data), plus status, command, and control registers, selected via two register-select address lines.
• Chip select conventions: CS0 is active-high and CS1 (written with a bar) is active-low; both must be asserted for the chip to respond, and datasheets often leave the bar/slash notation unexplained.
• Baud rate crystal: the 6551 derives standard baud rates from an external 1.8432 MHz crystal wired with a resistor and capacitor per the datasheet, rather than needing software timing loops.
• Programmed I/O (PIO) vs DMA: because the CPU is the only bus master in this design, every byte moves through the CPU (memory to register, register to device) rather than the device accessing memory directly, as DMA would allow.
• Address decoding with NAND gates: the computer already uses high address bits to select ROM, RAM, or the VIA; the new UART is added at address $5000 using a small NAND-based decode, with unused address combinations left off-limits to avoid selecting two chips at once.
• Data bus wiring mistake: a caught error where the eight data lines were connected in reverse order illustrates how a subtle wiring bug would corrupt every byte transferred without an obvious symptom.

Walkthrough

The cost of software-timed serial (0:00)

The lecture recaps the working but CPU-intensive bit-banged serial code, showing the calibrated delay loop needed to hit 104 microseconds per bit, and notes that changing baud rate would require redoing that calibration. It introduces the 6551 UART as the standard hardware solution and previews its datasheet, which supports 15 selectable baud rates and configurable word length, parity, and stop bits.

Chip select and pin conventions (2:00)

The lecture reads the 6551's pinout and block diagram, explaining the active-high/active-low chip select pair and the various notations (bar, bubble, slash) datasheets use to mark active-low signals, using the pin description text as the definitive clue when the symbol is ambiguous.

Wiring the RS-232 side and crystal oscillator (4:02)

Transmit and receive data lines connect through the existing MAX232 chip rather than directly, since RS-232 still needs the higher voltage swing. The lecture wires the 1.8432 MHz crystal, a 1 MΩ resistor, and a 30pF capacitor per the datasheet's recommended baud-rate-generator circuit.

Sharing the data bus and address decoding (7:03)

The lecture explains that all devices sharing the data bus must never drive it simultaneously, so the CPU stays the sole bus master (programmed I/O) rather than allowing direct memory access. It reviews how the existing ROM, RAM, and VIA address ranges are decoded from high address bits, then designs new NAND-based logic so the UART responds only to $5000-$5003, being careful that no address accidentally enables two chips at once.

Connecting control signals and finding a wiring bug (17:10)

Register-select lines, the read/write signal, the system clock, and reset are wired from the CPU and address bus to the corresponding 6551 pins, with the interrupt line left unconnected for now since it already goes to the VIA. While checking the wiring, the lecture discovers the eight data lines were connected in reverse order and fixes it, noting this bug would have silently corrupted every byte without an obvious symptom.

Registers ready, code to follow (20:11)

With hardware wired up, the lecture identifies the addresses for the data, status, command, and control registers and stops short of writing the initialization code, leaving that for a follow-up video and encouraging viewers to try configuring the registers themselves using the datasheet.

Before you watch

• The earlier videos in this series building the RS-232 receive and transmit routines in software, and the MAX232 charge-pump interface.
• Familiarity with the 6502 computer's address bus, data bus, and existing address decoding for ROM, RAM, and the VIA.
• Basic understanding of chip-select logic and datasheet pinouts.

Check your understanding

1. Why must the CPU remain the only bus master in this design, and what would direct memory access change about that?
2. How does the address decoding logic ensure the UART and the VIA are never both selected at the same time?
3. Why was the reversed data-bus wiring bug potentially hard to diagnose from symptoms alone?
4. What advantage does a hardware UART have over the earlier bit-banged serial code beyond simplifying the software?