Interrupt Handling with the 6522 VIA

What this lecture covers

The previous video's button-triggered IRQ had a problem: as long as the button was held down, the interrupt line stayed low and the handler kept firing, incrementing a counter hundreds of times per press. This lecture asks how to get one clean interrupt per button press using the 6522 versatile interface adapter (VIA) chip already wired into the breadboard 6502 computer, rather than the processor's raw interrupt pin.

By the end, you'll understand how the 6522's interrupt flag register, interrupt enable register and peripheral control register work together to detect an edge, signal the processor, and let the handler explicitly clear the interrupt, plus a simple software technique for absorbing switch bounce.

Key ideas

• The 6522 has its own interrupt pin: pin 21 (IRQ) on the 6522 connects to the 6502's IRQ pin, letting the VIA chip signal interrupts to the processor.
• CA1/CA2/CB1/CB2: four extra 6522 pins, beyond the 16 data pins on ports A and B, that can trigger interrupts on a signal transition.
• Interrupt flag register (IFR, $600D): read after an interrupt to determine which source caused it (timer, shift register, CA1, CA2, CB1, CB2).
• Interrupt enable register (IER, $600E): must be written to enable a specific interrupt source; bit 7 acts as a set/clear flag for whichever other bits are set in the same write.
• Peripheral control register (PCR, $600C): configures whether CA1/CB1 trigger on a positive or negative edge; the demo needs a negative edge since the button pulls the pin low.
• Clearing the interrupt: for CA1, reading port A clears the interrupt flag, which is what lets the processor return control instead of re-entering the handler immediately.
• Software debouncing: adding a delay loop inside the interrupt handler before clearing the interrupt lets mechanical switch bounce settle, at the cost of a sluggish response.
• Saving registers in a handler: because the delay loop uses X and Y, the handler must push and restore A, X and Y on the stack so it doesn't corrupt the interrupted program's state.

Walkthrough

Recap of the interrupt problem (0:00)

The lecture recaps the previous video's issue: a level-triggered IRQ button causes the handler to run repeatedly for as long as the button is pressed, and introduces the 6522 as a way to gain more control.

The 6522's registers (1:13)

A review of the 6522's existing use for LCD output via ports A and B, and their data direction registers, sets up the fact that many more registers on the chip exist, including several for interrupt handling.

Interrupt operation (3:03)

Referring to the datasheet, the lecture explains that the 6522's IRQ pin (pin 21) should be wired to the 6502's IRQ pin, and that reading the interrupt flag register after an interrupt reveals which of several possible sources (timers, shift register, CA1/CA2/CB1/CB2) caused it.

Interrupt flags and interrupt enable (4:44 and 6:39)

The button is rewired to the CA1 pin. The interrupt enable register is written with $82 to enable CA1 interrupts (setting both the enable/set bit and the CA1 bit), which is necessary before any CA1 interrupt will fire.

Interrupt control (peripheral control register) (9:02)

The peripheral control register is set to configure CA1 for a negative-going edge, matching the button pulling the pin low, and written with 0 since the other bits aren't needed for this setup.

Clearing the interrupt (12:19)

The handler is updated to clear the CA1 interrupt by reading port A (using a BIT instruction so the A register doesn't need saving), which stops the interrupt from re-firing continuously and lets the program resume normally after one interrupt per edge. Testing shows mostly single counts, with occasional extra counts from switch bounce.

Adding a delay (software debouncing) (17:06)

A nested countdown loop using the X and Y registers is added before clearing the interrupt, giving switch bounce time to settle. The handler now saves and restores A, X and Y via the stack, since the delay loop needs those registers. The result is more reliable single counts, but a noticeably laggy response.

Interrupt flag register in more complex systems (22:33)

The lecture closes by noting that this setup didn't need to read the interrupt flag register because only one source (CA1) was enabled, but explains that in systems with multiple VIA chips or multiple enabled interrupt sources, reading the flag register (and testing its top bit with a BIT comparison) becomes necessary to identify which source triggered a given interrupt.

Before you watch

• Watch the previous "Hardware interrupts" video, since this one directly fixes the level-triggered IRQ problem demonstrated there.
• Be familiar with the 6522 VIA's ports A and B and their data direction registers, already introduced for LCD output in earlier videos.
• Know how to push and pull the accumulator on the 6502 stack, used here to save X and Y indirectly.

Check your understanding

1. Why did the original IRQ-button setup increment the counter hundreds of times per button press, and what specifically fixes that in this lecture?
2. What do the interrupt flag register and interrupt enable register each do, and why are both needed?
3. Why does the peripheral control register need to be configured for a negative edge in this circuit?
4. What does reading port A accomplish for the CA1 interrupt, and why is a BIT instruction used instead of LDA?
5. What is the downside of the software debouncing approach used here, and what alternative does the lecture mention?