Lecture 23: Energy, CMOS

What this lecture covers

The previous lecture derived a power formula for a simple resistor-load inverter and left you with a homework calculation. This lecture opens by plugging in realistic numbers and showing that the result is absurd — hundreds of kilowatts per chip — which motivates a redesign. It then introduces the PMOS transistor and CMOS logic, the complementary NMOS/PMOS pairing that removes standby power almost entirely and became the basis of essentially all modern digital chips.

After watching, you can explain why a resistor-load NMOS inverter is impractical at scale, describe how a PMOS transistor's complementary switching behavior combines with an NMOS transistor to form a CMOS inverter with no direct path from supply to ground, and compute the dynamic power of a CMOS inverter using the same charge/discharge framework from the previous lecture.

Key ideas

• Standby power dominates in resistor-load inverters: plugging in realistic numbers (10^8 gates, 1 GHz, VS = 5 V, RL = 10 kOhm) into the static power term from the prior lecture gives about 125 kW total, dwarfing the roughly 250 W of dynamic power — an impossible design point.
• Increasing RL trades power for speed: raising RL lowers standby power but also slows the inverter's rise time, since the RC charging time constant grows with RL.
• PMOS (PFET) transistor: a P-channel MOSFET that turns on when VGS is less than or equal to a negative threshold voltage VTP, the electrical complement of the N-channel MOSFET (NFET), which turns on when VGS is greater than or equal to a positive VTN.
• CMOS inverter structure: replacing the load resistor with a PMOS transistor (the pull-up) paired with the existing NMOS transistor (the pull-down) means exactly one of the two is on at any time, so there is never a direct current path from supply to ground.
• Zero idealized standby power: because CMOS logic has no direct supply-to-ground path when idle, its standby power is zero in the idealized model — the main motivation for adopting it industry-wide.
• CMOS is also faster: the effective "pull-up resistance" becomes the PMOS on-resistance, RONp, which can be made small, instead of a large fixed RL, giving rise and fall times of similar, smaller magnitude.
• Dynamic power formula carries over unchanged: using the same charge/discharge analysis as the prior lecture, CMOS dynamic power is C*VS^2*F, with no RL term, since the result is independent of the on-resistances as long as T1 and T2 are much longer than their respective time constants.
• Lower voltage and idling further cut power: dropping supply voltage from 5 V to roughly 1-1.5 V cuts power by the square of the ratio, and idling unused functional units (stopping their clock) proportionally reduces the time-averaged power.
• Real chips still leak: even ideal CMOS logic has no standby path, but real transistors have leakage currents that produce a nonzero standby power in practice.

Walkthrough

Revisiting last lecture's power numbers (2:07)

The lecture recaps the inverter power formula from the previous session, split into a frequency-independent standby term and a frequency-dependent dynamic term. Plugging in the assigned numbers — 10^8 gates, 1 GHz, C = 0.1 femtofarads, VS = 5 V, RL = 10 kOhm — yields roughly 1.25 mW standby and 2.5 microwatts dynamic power per gate, which scale up to about 125 kW standby and 250 W dynamic for the whole chip. The 250 W figure is compared to a real Pentium 4's 170 W draw at launch as a sanity check, while the 125 kW standby figure is flagged as clearly unworkable.

Why simple fixes don't work (7:14)

The lecture asks what could be changed to reduce this standby power. Increasing RL reduces power but slows the inverter, since the charging time constant is proportional to RL. Reducing supply voltage only cuts power by the square of the voltage ratio and isn't enough on its own. This sets up the need for a structurally different design.

Building intuition for a complementary switch (10:16)

Examining the inverter's on and off states separately, the lecture observes that when the input is low, the NMOS switch opens and standby current is zero — the desirable case. The insight is to ask whether the load resistor could similarly "open up" when the input is high, eliminating the other standby path. This motivates looking for a device whose on/off behavior is complementary to the existing NMOS transistor.

Introducing the PMOS transistor (15:27)

The lecture reviews the NMOS transistor's switching rule (on when VGS >= VTN) and introduces the P-channel MOSFET (PFET), which turns on when VGS <= VTP for a negative threshold VTP. A worked numeric example (source at 5 V, VTP around -1 V) shows the PFET turning on only when the gate voltage drops below about 4 V, the complement of the NFET's behavior.

Assembling the CMOS inverter (19:39)

Replacing the load resistor with a PMOS transistor creates a pull-up device paired with the existing NMOS pull-down device. Working through both input states (VIN = 5 V and VIN = 0 V) shows that in each case exactly one of the two transistors conducts and the other is fully off, so there is never a direct current path from the supply to ground. This structure — complementary NMOS and PMOS pull-down and pull-up — is named CMOS (complementary MOS) logic, described as the basis of essentially all modern digital chips.

Computing CMOS dynamic power (25:51)

Modeling the CMOS inverter driving a capacitive load with a periodic input, the lecture reuses the charge/discharge equivalent circuit from the prior lecture, now with RONp for charging and RONn for discharging instead of a fixed RL. Because the earlier derivation showed the result is independent of resistance value when the charge and discharge times are long compared to their time constants, the same average dynamic power formula, C*VS^2*F, applies directly, with no RL term at all.

Revisiting the numbers and further power tricks (32:04)

Recomputing the example gives 250 W for a 10^8-gate, 1 GHz chip with no standby term — high for a laptop but reasonable for a desktop with a fan. The lecture notes that rising clock frequencies (projected toward 5-10 GHz) would push this toward kilowatts if nothing else changed, but that supply voltage has dropped over generations from 5 V toward roughly 1-1.5 V, cutting power by a large factor. It also introduces "idling" — turning off the clock to unused functional units so they don't switch at all — as a further way to cut average power, and closes by noting that real CMOS transistors leak current and so do have some nonzero standby power in practice, followed by a demonstration heating an inverter until it fails.

Before you watch

• Watch Lecture 22 first: this lecture continues its inverter power derivation and reuses its charge/discharge power formula directly.
• Be comfortable with the NMOS transistor's on/off switching condition (VGS versus a threshold voltage VT), since the PMOS device is introduced as its complement.
• Recall the standby-power and dynamic-power terms of the resistor-load inverter formula, since this lecture starts by plugging numbers into them.

Check your understanding

1. Why does the resistor-load inverter's standby power dominate its dynamic power once realistic gate counts are plugged in?
2. How does a PMOS transistor's turn-on condition differ from an NMOS transistor's, and why does that make them complementary?
3. Why is there never a direct current path from supply to ground in an idealized CMOS inverter, in either input state?
4. Why does the CMOS dynamic power formula C*VS^2*F not depend on RONn or RONp, as long as T1 and T2 are long enough?
5. Name two techniques, besides switching to CMOS, that reduce a chip's power consumption, and explain briefly how each works.