Lecture 1: Intro, Transistors, and Gates

What this lecture covers

This opening lecture of Digital Design and Computer Architecture sets up the course and then starts the technical material from the bottom of the stack. Onur Mutlu explains why the course studies computers from transistors up through microarchitecture, and why that grounding matters even if you end up working purely in software: without knowing what the hardware actually does, you can't reason well about performance, safety, or efficiency.

After the logistics, the lecture moves into the first technical content: what a MOS transistor is and why it can be treated as a simple voltage-controlled switch, then how pairs of n-type and p-type transistors are wired into CMOS logic gates. By the end you can explain why an inverter, a NAND gate, and an AND gate are built the way they are, and you're ready for combinational logic in the next lecture.

Key ideas

• Transformation hierarchy: a problem is turned into an algorithm, then a program, then translated across the software/hardware interface (the ISA) into microarchitecture, logic gates, transistors, and ultimately electrons.
• ISA vs. microarchitecture: the instruction set architecture (ISA) is the contract between hardware and software; microarchitecture is one of many possible implementations of that contract.
• General-purpose vs. special-purpose design: CPUs are flexible but less efficient; ASICs (like Google's video-encoding chip) are efficient but inflexible; GPUs and FPGAs sit in between.
• MOS transistor as a switch: applying the right gate voltage makes the source and drain act like a connected wire (closed circuit) or a disconnected one (open circuit), like a wall switch.
• n-type vs. p-type: an n-type transistor closes (conducts) with a high gate voltage; a p-type transistor closes with a low gate voltage — they behave oppositely.
• Pull-up and pull-down: p-type transistors are good at pulling the output up to the high voltage; n-type transistors are good at pulling it down to zero.
• CMOS inverter (NOT gate): one p-type transistor (pull-up) and one n-type transistor (pull-down) sharing an output produce Y = NOT A.
• NAND before AND: a NAND gate is built directly from parallel p-type and series n-type transistors; an AND gate is a NAND gate followed by an inverter, because a fully parallel pull-up network for AND would not work reliably.

Walkthrough

Course introduction and research context (0:00)

The lecture opens with introductions: Onur Mutlu, his co-instructor, and the teaching assistants. Mutlu describes his research on making computers more efficient, robust, and secure, and previews the "expanded view" of computer architecture the course will use — where hardware, algorithms, and system software are co-designed rather than optimized in isolation. He connects this to examples like specialized matrix-multiplication hardware for machine learning and mentions DeepSeek as an example of squeezing efficiency out of understanding hardware and software together.

The transformation hierarchy (22:16)

Mutlu asks why computers exist and lands on "to solve problems," then walks through how a problem actually gets solved by electrons: it's translated into an algorithm, a program, system software, the software/hardware interface (ISA), microarchitecture, logic, and finally devices. This hierarchy is the map for the whole course. He also defines computer architecture as the science and art of designing computing platforms to meet a set of goals, and stresses that different systems (a supercomputer, a phone, a general-purpose laptop) optimize for different, sometimes conflicting, goals such as performance, battery life, and cost.

Course goals, design goals, and today's heterogeneous systems (26:19)

The lecture surveys real systems — CPUs, GPUs, wafer-scale AI chips, self-driving car processors, in-memory processing chips — to show how much heterogeneity exists in modern computing compared to the CPU-dominated era Mutlu studied in. He contrasts general-purpose designs (flexible, easier to program, lower peak efficiency) with special-purpose ASICs (efficient at one task, hard to program, inflexible), using an adjustable wrench versus a fixed wrench as an analogy. He notes that industry and research are both in the middle of a paradigm shift toward more specialized, heterogeneous hardware, and situates the course's labs, in which students build a simple processor on an FPGA using Verilog.

The MOS transistor as a switch (1:20:22)

Mutlu introduces the MOS (metal-oxide-semiconductor) transistor and explains that the course treats it as an abstraction: a switch with a source, drain, and gate. The electrical details are deliberately left to a microelectronics course; what matters here is the switching behavior. He distinguishes n-type transistors, which close the circuit when the gate voltage is high, from p-type transistors, which close when the gate voltage is low — the opposite of each other. He reinforces this with the wall-switch-and-lightbulb analogy: current must flow in a closed loop from a power supply through the switch to a lamp and back for the lamp to light.

Building the CMOS NOT gate (1:30:29)

Combining one p-type transistor (connected to the high voltage) and one n-type transistor (connected to zero volts) at a shared output produces the simplest CMOS gate: an inverter. Mutlu traces both input cases: with a low input, the p-type transistor conducts and pulls the output high; with a high input, the n-type transistor conducts and pulls the output low. He builds the truth table from this transistor-level reasoning and introduces the rule of thumb that p-type transistors pull up and n-type transistors pull down, along with the bubble notation used to show inversion in gate diagrams.

NAND and AND gates (1:37:38)

Extending the same idea to two inputs, Mutlu builds a gate with two p-type transistors in parallel (pull-up network) and two n-type transistors in series (pull-down network). Working through all four input combinations shows the output is high unless both inputs are high, which is the NAND function, NOT (A AND B). He explains that an AND gate is then built as a NAND gate followed by an inverter, rather than directly, because a "direct" AND circuit using the complementary transistor arrangement would not switch reliably — p-type transistors are poor at pulling outputs up when wired the other way. He closes with the general CMOS gate template: a p-type pull-up network and an n-type pull-down network sharing an output, with parallel transistors turning a network on if any one of them conducts and series transistors requiring all of them to conduct.

Before you watch

• No prior computer architecture knowledge is assumed; basic binary numbers help but aren't required for this lecture.
• Nothing from earlier lectures in this course is needed, since this is Lecture 1.
• It helps to have seen the idea of a transistor or logic gate before, even informally, though the lecture explains both from scratch.

Check your understanding

1. What is the transformation hierarchy, and where do the ISA and microarchitecture sit within it?
2. Why does the lecture use a MOS transistor's switching behavior as the lowest level of abstraction rather than going into device physics?
3. Explain, in terms of pull-up and pull-down networks, why the output of the CMOS inverter is high when the input is low.
4. Why is an AND gate built as a NAND gate followed by an inverter instead of directly from parallel p-type and series n-type transistors?
5. What trade-offs distinguish a general-purpose CPU from a special-purpose ASIC, and where do GPUs and FPGAs fall between them?