Lecture 10: Microarchitecture Fundamentals and Design II

What this lecture covers

This lecture builds a complete single-cycle MIPS microarchitecture from first principles: it answers how a data path (the hardware that moves and transforms data) and control logic (the hardware that decides what the data path should do) are constructed instruction by instruction, and then asks whether a single-cycle design is actually a good idea. It follows directly from the previous lecture's ISA-versus-microarchitecture discussion and the outline of single-cycle versus multi-cycle machines, and it sets up the multi-cycle design covered in the next lecture.

You'll watch the data path grow incrementally as R-type, I-type, load, store, jump and branch instructions are added one at a time, see how control signals are derived for each instruction, and then work through a concrete performance calculation using assumed component delays. After watching, you should be able to explain why a single instruction's data path requires specific wires and multiplexers, compute which instruction determines a single-cycle machine's clock period, and state the three microarchitecture design principles the single-cycle approach violates.

Key ideas

• Data path vs. control logic: the data path consists of functional units (ALU), storage (registers, memory) and interconnect (wires, multiplexers) that operate on data; the control logic generates the signals that tell the data path what to do with that data.
• "Do no harm": when adding an instruction's data path, any hardware not needed by that instruction must be left in a state where it cannot corrupt architectural state, such as disabling register writes or memory writes.
• Execution time equation: total execution time equals (instructions executed) x (average cycles per instruction, CPI) x (clock cycle time); at the microarchitecture level, given a fixed instruction count, only CPI and clock cycle time are free to optimize.
• Single-cycle's fixed CPI: by definition every instruction takes exactly one cycle (CPI = 1), so the only lever left is clock cycle time, and multi-cycle designs trade a higher average CPI for a much shorter clock cycle.
• Critical path determines cycle time: the clock cycle must be long enough for the slowest instruction, so in the lecture's worked example lw (600 picoseconds under the given assumptions) sets the cycle time even though jump only needs 200.
• Hardware replication cost: because everything must happen in one cycle, any resource an instruction needs more than once (or that different instructions need concurrently) must be duplicated, making single-cycle designs also hardware-inefficient.
• Three microarchitecture design principles: critical path design (shorten the worst delay), common-case design (optimize for frequent operations), and balanced design (avoid bottlenecks by matching resources to workload) — all three are violated by the single-cycle approach.
• Multi-cycle's core idea: let each instruction take only as many cycles as it actually needs, storing intermediate results in microarchitectural registers, which decouples clock cycle time from any single instruction's total latency.

Walkthrough

Recap and the data path/control split (4:01)

The lecture reintroduces the single-cycle model from the previous lecture, where architectural state transforms into new architectural state in one clock cycle, and formally splits an instruction processing engine into a data path (functional units, wires, storage) and control logic (the circuitry that generates signals telling the data path what to do). It also contrasts single-cycle and multi-cycle machines in how control signal generation can or cannot be overlapped with data processing.

Performance equation and the CPI trade-off (21:15)

Before building the data path, the lecture establishes the performance framework: execution time is the sum, over all executed instructions, of cycles-per-instruction times clock cycle time, which can also be written as instruction count times average CPI times clock cycle time. It explains that single-cycle designs fix CPI at one, leaving no freedom there, while multi-cycle designs allow trading a larger average CPI for a much shorter clock cycle, giving two independent knobs to optimize.

Building the data path for R-type and I-type ALU instructions (34:24)

Starting from a program counter, instruction memory and register file, the lecture adds the wiring needed to execute an add R-type instruction: reading two source registers, computing the ALU result, and writing it to the destination register while incrementing the PC. It then extends this to I-type instructions, which need a sign-extended immediate and a different destination register field, requiring new multiplexers controlled by an "is I-type" signal to select between register and immediate operands and between the two possible destination register encodings.

Adding loads, stores, jumps and branches (41:27)

The data path grows further to support lw (compute an address, read data memory, write the result to a register) and sw (compute the same address but write a register's value into memory instead), with a new multiplexer selecting whether the register file's write data comes from the ALU or from memory. For the unconditional jump, the lecture stresses a common design mistake: the jump target must be built from the incremented PC, not the raw PC, illustrating how easy it is to violate the ISA specification when connecting the wrong wire.

Conditional branch data path (1:06:02)

Branch instructions require computing a target address (PC + 4 + sign-extended, shifted immediate) with a dedicated adder, comparing two register values in the ALU, and using the comparison result to control a multiplexer that selects between the branch target and PC + 4. The lecture notes this is the first case where a control signal for the data path depends not only on the instruction's opcode but also on a value computed by the data path itself.

Generating control signals (1:14:07)

With the full data path assembled, the lecture derives each control signal as a function of the opcode and function-code bits, for example how RegDst picks the destination-register field, how MemToReg selects the register file's data input, and how RegWrite is asserted for every instruction except store, branch and jump. It notes that control logic can be implemented as hardwired combinational logic or as a memory-based control store, both of which appear in real processors.

Evaluating the single-cycle design (1:27:22)

Using assumed component delays (200 ps for memory, 100 ps for the ALU and adders, 50 ps per register file access), the lecture computes per-instruction critical paths and finds lw at 600 picoseconds versus jump at 200, showing the whole machine must run at the slowest instruction's speed. With realistic memory latencies the gap would be far larger. This motivates the conclusion that single-cycle designs are contrived, hardware-inefficient, and unable to optimize for common instructions, violating critical-path, common-case, and balanced design principles.

Before you watch

• Review the single-cycle versus multi-cycle overview and the six-step instruction processing cycle from the previous lecture in this course.
• Be comfortable with combinational logic timing analysis (critical path, setup/hold time) from the earlier digital design lectures.
• Know MIPS instruction encoding (R-type, I-type, opcode and function fields) since the data path is built directly from these bit positions.

Check your understanding

1. Why does adding I-type instructions to an existing R-type data path require a new multiplexer in front of both the ALU's second input and the register file's destination-register input?
2. What mistake does the lecture warn against when wiring the jump target address, and why does it violate the ISA specification?
3. Given the lecture's assumed component delays, why does lw become the critical-path instruction, and how does that determine the whole machine's clock cycle time?
4. Which of the three microarchitecture design principles (critical path, common-case, balanced design) does the single-cycle design violate, and how does a multi-cycle design address each one?